CAREER SUMMARY:

Intelligent, responsible, creative Senior Design Engineer recognized for solid knowledge of device and design flows. Seeks environment in which to analyze and solve problems while working on leading edge designs as a Frontend or Backend Design Engineer. Has particular expertise in: Block/SOC level reliability verification and mixed signal verification Power grid design and robustness check of grid Extensive Spice modeling for circuit analysis Physical design and floor planning, Low power circuit design and techniques, Device modeling

COMPUTER/SOFTWARE SKILLS:

Industry tools: StarRC, Hercules, Apache Totem/Redhawk, ultrasim, Pathfinder, cadence, XA, Caliber, Prime time, Platocbd, DC and Confidential .

Design Software: SILVACO, SCHRED, Cadence, Mentor Graphics, MAGICSimpleScalar, VHDL, HSpice, IRSim, OrCAD, Pspice, Matlab, MathCAD, Tecplot.

Operating Systems: UNIX, Linux, Windows.

Languages: FORTRAN, C, System verilog,Visual BASIC, HTML, Perl, TCL/TKLATEX.

PROFESSIONAL EXPERIENCE:

Confidential

Senior design Engineer

Responsibilities:

• Worked on five different atom based SOC products and have hands on experience on Confidential floor planning, finalizing bump map and power grid robustnesschecking.
• Have experience in cross - site cross-team environment. Used spice modeling for CPM (chip power modeling) .
• Spice modeling is used to estimate the custom circuit register files dynamic current profiles. Spice modeling is used in mixed signal simulation for generating analog block model in spice.
• Low power analyses were also performed using the spice model of the circuit.
• Reliability verification works as design Engineer on FULL chip/block level: Owned the Confidential RV (IR EM and SH) analysis on atom based SOC product code name Moorestown.
• Basically performed power and signal robustness checking. Executed extensively Confidential static and dynamic IR drop analysis, Confidential EM analysis using Redhawk and SH analysis using netrvCBD. Performed transient analysis (ramping up or ramping down one block while the other blocks are in active mode) using Redhawk tool.
• Developed and Ran CPM modeling in order to estimate R die and Cdie of Chip using Redhawk tool.
• Ran Block level IR drop on GFX block, register files etc.
• Used Spice Modeling for the register files for Atom based latest SOC product for generating dynamic current profile using Totem after doing lot of circuit simulations. Reliability verification works on FULL chip/block level: Developedvalidated the Reliability Verification flow (EM,SH and IR drop) based on drive and supported the customer across the board in Atom team and released the new version whenever it was available and finalized POR version for tool.
• Resolved different issues that were related to RV tools for tool enhancements.
• ESD flow Work: Performed ESD verification on atom based SOC product for verifying the Confidential level clamp placement and latchup condition. Developed, validated the ESD verification flow and supported the customers across the board in Atom team and released the new version whenever it was available and finalized POR version for tool. RFS memory/circuit design works: Designed and developed Custom
• Register file for atom based product.
• Developed the schematic, layout, ran lvs, did the formal equivalence check, performed timing analysis, ERC and rv analysis i.e. from rtl to gds file generation for RFS. Ported the bit slice schematic for RF from earlier version. Made the necessary transistor adjustments and scaling.
• Mixed signal verification works on block level: Analyzed the analog/custom circuit functionality to insure that both RTL and circuit designers correctly implemented the circuit specification and that the circuit complies with all required external and platform specifications using Verilog AMS model.
• Used full featured standalone next generation transistor level simulation engine XA that delivers SPICE accuracy while maintaining Fast-SPICE performance and capacity.
• Implemented design improvement, tool and methodology refinement in RTL model and SPICE NETLIST, Validated design by identifying and exercising special cases for specific test, Debugged performance issues and test failures and provided robust functional fixes, Developed dedicated verification environments and tools using UNIXwhile driving a complex process of exercising the design to verify its logical correctness.
• Authorized and implemented test plans to provide test coverage for new architecture features system verilog, Strong discipline and attention to detail in ensuring effective and high quality validation that minimizes bug escapes and fixes. Digital verification works:
• Developed SystemVerilog UVM testbenches for block-level functional verification of units Created and maintained detailed verification plans and reviwed with the stakeholders.
• Generated and ran testcases on logic simulation models Debugged functional errors in the RTL model, using simulation toolsdebug tools and based on in-depth understanding of the architecture and RTL design.
• Defined and implemented functional coverage, and enhancing the testbench to ensure coverage closure.

Confidential

Component Design Engineer

Responsibilities:

• Finalized the bitcells for the Ultra low leakage and mixed gate (MXRF) register file arrays for smaller gate length RF.
• Ran extensive stability simulations for various PVT corners to estimate the defect margin and Vmin.
• Develop the stability model for MXRF which has thick gate devices
• Ported the bitslice schematic for MXRF from earlier version.
• Made the necessary transistor adjustments and scaling.
• Simulated critical read and writetimings for the MXRF and ULL arrays using Cougar for various performance PVT corners.
• Ran Idle and drowsy mode leakage simulations SRAM bitcell through internal circuit simulator.
• Worked on Estimations of leakage for a number of compiled SRAM and Register file arrays for different gate length.