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Circuit Verification Intern Resume

Sunnyvale, CA


  • 9+ months of industry experience as Hardware Engineering Intern; used Verilog (Model/Questa Sim), Python(Spyder), UVM
  • Completed 9+ projects utilizing Verilog, SystemVerilog, Virtuoso, VCS, NC - Verilog, Quartus Prime, ModelSim, Xilinx ISE


Technical Skills: Verilog, SystemVerilog, UVM, Python, VHDL, Matlab, Perl, C, Linux, Assembly language, Excel, Word

Technologies: Simulation, Debug, Functional Verification, Static timing Analysis, Logic Synthesis, Place & Route, Cadence Virtuoso

Others: SPI, I2C, UART, PCAT, AXI, DFT, JTAG, SCAN, BIST, Spyder, GVIM, Coverage, Assertions, GIT, Lint, Makefile, CDC


Circuit Verification Intern

Confidential, Sunnyvale, CA


  • Created & Verified Verilog models for PVT Sensor, SCAN, PLL, XTAL oscillator, SSCG, using Model/Questa Sim
  • PLL & Sensor IP PVT characterization, power, HTOL, using Spartan-6 FPGA, Xilinx ISE; Opal Kelly board bring-up
  • Created Emulation, CTL, UPF, Stub-Verilog, Power Aware, TetraMAX models; made data analysis plots using Python

Hardware Test Engineering Intern

Confidential, Santa Clara, CA


  • USB2.0/3.0 SS, HS, FS, LS, interop, PET, CV, Link-layer Electrical Compliance testing, using e/xHCI, MSO, DSA, DMM
  • Functional (Pre)- testing of Thunderbolt3.0, on Mac & Windows, involving PCIe, Ethernet, SSD, daisy-chaining

Instructional Student Assistant

Confidential, San Jose


  • Assist Professor, in "Digital Circuits" course, with grading exams, homework, & labs of 100+ undergrads, involving VHDL

Transaction Risk Investigator



  • Developed input port module using state machine & instantiated it 32 times using generate statement
  • Implemented FIFOs, CRC, along with arbiter & ingress scheduler to control input traffic to memory
  • Controlled memory interfacing & allocation with respect to FIFOs’ & memory’s statuses
  • Designed DUT and Stimuli (sequence) wrappers; used ports, exports, fifos, timestamps, queue of messages
  • Created UVM test, environment, agent, 64 messages (queue and timestamp), 64 monitors, 32 scoreboards
  • Designed varying frames, CRC, bit stuffing, and bit timing to facilitate serial message transfer, viz., APB
  • Designed AHB’s slave mode (APB) and master mode; Designed Multi-Master AHB using arbiter, mux, decoder
  • Implemented RTL design & performed functional & timing verifications for synthesis; analyzed total time delay, power
  • Developed parametrized (Generic) code for sequential multiplier; analyzed number of clock cycles, clock period, area
  • Used IP libraries to implement RAM, multiplier, & adder blocks; implemented circular buffer in RAM blocks
  • Implemented parsing, rounding & saturation logic, for DSP signals; Increased performance by running 4/16 MACs in parallel
  • Improved Adaptive FIR filter performance by executing both FIR and LMS operations in parallel
  • Built & generated system using Qsys; compiled to burn file on board; programmed system by creating workspace

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