SUMMARY

• One plus year of experience with Nuclear V model HLCD for Verification and Validation and Environmental Qualification support.
• Sixteen years as a design engineer and over 6 years of EMC and EMI experience with skillful knowledge of LabView, CST tools, pre - compliance testing according to internal test methods, performing simulations, running tests, analyzing and reporting status.
• Expert knowledge in the Life Cycle Development SDLC, HDLC, QTP, ITAR, QTR and Verification, Validation, Design, Software.
• Over 10 years of adept experience with of CAD / CAE tools / mentor graphics.
• Over 10 Years of Analytical approach to problem solving and POC.
• Experience in the design of ASIC, FPGA design, simulation, VHDL, HDL, Verilog, Specman E, Vera, RVM, SystemVerilog, HVM, OVM, OVC, CDV, TLM, VMM, API, RTL level modeling, DFT and Verification: methodology requirements, Testbench generation.
• Experience in the design and testing of EMC and EMI effect related to the electromagnetic phenomena on a product function operation. I applied test standards RTCA DO-160D EUROCAE ED-14D, and Mil-Std 461 E to test confirmative to the avoidance of any interference effects on the correct operation of a product.
• I have design and development experience of active/passive circuits such as, filters, Transmission Lines, phase shifters, amplifiers (LNA), oscillators and mixers for RF-to-IF conversion designs.
• I have applied good oral/written communications skills, with the ability to analyze and resolve integration problems; demonstrate individual initiative, when working as part of a project team.
• Have skills in Project Management and the development of products, as well as customer support training.

TECHNICAL SKILLS

Revision Control Software: ENOVA, Peer, PAACE, ClearQuest, TDM, ClearCase, Perforce, Omnify, Source Safe, RCS, Remedy, CVS and PLM.

Computer Systems: Sun, HP-UX, Apollo, DEC, VAX, IBM, Cyber 170 and PC's.

Operating Systems: UNIX, DEC Windows, Macintosh, VMS, MS Windows, MS DOS.

Navigation System: ADS-B, SATCOM, AWOS and GNSS.

Design Languages: VHDL, HDL, OVM, VMM, UVM, AVM, RVM, Verilog, Vera, E, System Verilog, VSV, SystemC, Specman, Makefiles.

Programming Languages: Perl, TCL, C/C++, and C #, SQL, Pascal, MathCAD, Radspice and Fortran.

CAE Software: MS Visual, Altium, Chip Scope, MatLab, Allegro, LabView, TestStand, ModelSim, Quartus, Code Coverage, Libero, SmartTime, Simplify, AutoCAD, FlashPro, Vera, Specman, Synopsis, PrimeTime, Visual HDL, Mentor Graphics, Concept, Cadence, V-System, NCsim, Renoir, Leonardo, OrCad, Max Plus, Synplicity, Galileo, Xilinx, Actel, Altera, VCS, Chip Express, Code Coverage, Static Timing, Omnisys, EEsof Touchstone, Libra, ICgraph, Academy, Silver- Lisco, Mainsail, Zycad, CALMA, CDC-MIDAS and Network CAD tools.

PC Software: DOORS, Slate, Microsoft Word, Excel, Powerpoint, Access, Project and Visio

Emulators: Lauterbach Trace 32

Specification's Familiar with: SAE ARP 4745A, ARP4754, IEEE 1012, 829, 7-43.2, 1149.1, RG 1.180, 1.209, EUROCAE, RTCA, Do-178B, 160, 254, ByetFlight, RS422, RS232, 485, PCI 1650, SPI, ARINC-429, 453, 461 E, 810 F, 600, 610, 615A, 615, NTSC, CANBUS, LIN, I2C, Ethernet, Rapid IO, USB, Smart Card, SPI3, AMBA, AHB, Firewire Fiber Channel, Ethernet, 802.1, 802.11,DFT, JTAG, BIST, LVTTL, LVDS, SSTL, Jbus, FEMA, CDR, PDR, MTBF, FHA, FTA, EMI and EMC.

FPGA: Xilinx -Virtex-4, Virtex-5, Actel, Altera Stratix-II XILINX ISE 10.1, Virtex- 2, 4 & Virtex - 5, Actel APA-750, Altera FLEX 10k/20k CPLD & Stratix -II -GX Devices

Microprocessor: Intel x486, 386, X86, Pentium - II & III, PowerPC-8270, 8051, 405, 440, RISC, Motorola, ARM, Texas Instruments - DSP's (C6X & C7X) and Microcontroller.

PROFESSIONAL EXPERIENCE

Confidential, Wilmington, NC

V&V Test Engineer Consultant

Responsibilities:

• My role for one plus year was working with Nuclear V model HLCD system level Verification and Validation. I provide Validation support for HSIS, HRS, HDD and VHDL based on function requirements Project schedule I worked as a test team member for system product validation testing. Lead project setup test, traceable, validation and documentation for test reporting. I provided test solutions on failed LRU boards to determine root failures.
• Verified and validates solution based on LUR testing. I completed Verification of firmware software testing and documentation to support SourceSafe revision control testing. Completed technical review of hardware project documents based on GEH, IEEE, NRC and other industry specifications. Lead project on the generation of Technical Design Procedure that outlines the development of a methodology for testing Complex Integrated Electronic FPGA’s, CPLD’s, PLD’s and schematic updates using Allegro.
• I worked on generating Environmental Qualification for components and system level products. I was responsible for the generating product Environmental Qualification Test Plans, Test Procedure, testing and scheduling equipment resources.

Confidential, Fort Worth TX

DO-254 V & V Consultant

Responsibilities:

• My role was a Firmware Do-254 and SAE ARP4745 A V&V support engineer for Fly by Wire IIM system. Provide technical support on issues of FAA and EASA Certification. I provide Validation support for QTP, QTR, HRS, HDD and VHDL based on Project schedule.
• Lead project audit reviews on system level requirements related to function, form, consistent, traceable, verifiable and clearly for IIM firmware hardware system requirements based on spreadsheet and SQL database files. I controlled tracked and documented the validation process on the IIMHRS, IIMHDD and VHDL code trace. I generated ICD documents to support IIM interface conductivity between Type A, B and C FPGA interfaces.
• I provided technical knowledge to perform complex analyses requiring supporting design, proof of concept POC, specification compliance, airplane certifications, support, and product development experience in composite.

Confidential, Lake Mary, FL

OVM Verification Consultant

Responsibilities:

• I was responsible for OVM, Verilog, C++ and Perl, PerlLog DFT design verification in Unix System and Product Environment. In this role I'm also responsible for verification of OOP design principles in a Product Level System Environment. I worked on the development of new product testbench development integration.
• Derived system level designed re-usable DFT Test Macro, IP for RTL testing. I modified Perl and Makefiles script files and executed test files for verifying testbench bugs in a top level SystemVerilog and Open Verification Methodology OVM System environment t.
• I implemented random constrained stimulus methodology to maximize functional coverage results. I generated functional coverage and code coverage reports using VCS. Tracked ECO testbench bug issues and ECO update release using revision control.

Confidential, Cedar Rapids, IA

System Engineer Consultant

Responsibilities:

• Responsible for the ITAR System EMC, EMI and ENV Qualification support on Mil-Std products programs. I applied test standards EUROCAE ED-14D, and Mil-Std 461 E to test confirmative to the avoidance of any interference effects on the correct operation of a display unit.
• Support FTE test station build and test station checkout. Lead project Qualification test suit to support EMC, EMI and ENV Qualification testing for the MDI and MDRI Unit. I integrated avionics Product Qualification testing for Mil-Std 461 E and 810 F testing integration.
• Generate test plans review for software modification and LabView test. I ran test 1 and 2 regression testing on units during Qualification testing. I completed Life Cycle Development SLCD process to

Confidential, Livonia, MI

V & V Engineer

Responsibilities:

• My role is responsible for Validation and Verification on A400M aircraft Floor Based Handing System product and ITAR. In this role I'm also responsible for validation of derived system and hardware requirements, inspection, FEMA, MTBF, FHA, FTA and Validation and Verification analysis.
• I generated DOORS requirements, support for Validation analysis and Verification requirements tracking. Verification using DO-254 practices. Retain the generation of Testbench generation using VHDL. Utilize the Freescale MPC8270

Confidential, Phoenix, AZ

Systems Engineer

Responsibilities:

• My role is responsible for Verification on Confidential aircraft Flight Control product. In this role I'm also responsible for validation of derived design hardware, inspection, and analysis of analog ATP for TVO generation.
• Generated MatLab simulation and mathematical models for Signal Analyzer to test analysis, proof of concept POC and verification system level requirements. I generated TVO test requirements for both the ComAux and MonAux design boards.
• Task as the intermediaries between the tests technician and Hardware Engineering to ensure TVO requirements testing are met. Responsible for all hardware related DO-160, PDR, CDR, BOM and DO-254 product system requirements based on ARP4754.

Confidential, Phoenix, AZ

Systems Engineer

Responsibilities:

• My role is responsible for GAP Audit of VM Methodology as define in the Life Cycle Product Develop Plan. This audit covered the review of all FRD FPGA Requirements Document, VDC Local Bus FPGA Verification Design Container, VTR FPGA Verification Test Results, VTP FPGA Verification Test Procedure, HVP Hardware Verification Plan, DVV Development, Verification & Validation Plan, DDD FPGA Device Design Document, PDC PLD Design Container Local Bus FPGA, HRD Hardware Requirements Document, VDD Local Bus FPGA Version Description Document, AID Local Bus FPGA Altered Item Drawing, and HDVP Hardware Development and Verification Plan.
• This review tested VM Methodology and it implementation within requirement specifications. In this role I'm also responsible for Systems Gap Audits and

Confidential, Phoenix, AZ

Design Engineer

Responsibilities:

• My role is responsible for MKIIIG and MKII+ CMU LRU systems development and verification. In this role I'm also responsible for Systems requirements, validation of derived hardware requirements for LRU, Plan for Hardware Aspects of Certification (PHAC), unit system test pre-build, FEMA, FHA, FTA, FFPA, safety analysis, Lead project product Unit Qual and overall certification for product release.
• I applied test standards RTCA DO-1, 60D and EUROCAE ED-14D to test confirmative to the avoidance of any interference effects on the correct operation of a LRU product during Product Qualification testing. I assisted in the generation of traceability system requirement for product, design and FPGA.
• I worked on the verification and VHDL test code of the new I/O card. Develop verification testbench to support block module for I/O PCMCIA, Ethernet for OVM Verification Methodology using SystemVerilog on a ModelSim simulator. Work on FPGA Lauterbach Trace 32 board integration for Ethernet, RS422, RS232, ARINC-429, 453, 600, 610, 615A, 615CANBUS, LIN, I2C, SPI, AMBA, AHB, SpaceWire, Rapid IO, Firewire, LVTTL, LVDS, SSTL input, Jbus, JTAG interfaces for a microcontroller.
• Team Lead in prioritizing workload, schedule resources, and provide technical direction to software test team. Lead Systems Engineer will support the PSSA and final SSA test requirements. Play the Intermediaries between the Customers Production, Test Engineering, QA, DOR and Hardware Engineering to ensure product requirements are met.
• Responsible for all hardware related DO-160E, DO-178B, DO-254, PDR, CDR, SATCOM, AWOS, GNSS, FMS, BOM and Qualification product level system requirements. Project role covered the lead support of five departments across four states and one Non US Department.

Confidential, Norcross, Georgia

Verification Consultant

Responsibilities:

• Responsible for firmware Do 254 Design Verification of two FPGA HDL Video CPLD's on a two month contract. I completed generation of Hardware Requirement Document and Hardware Verification Plan for a Video Frame Buffer Controller, as well as for a NTSC Frame Buffer project and test bench environment directory using C++ and VHDL for testing to verify proof of concept.
• I completed FPGA JTAG testing and design verification for two Video Buffer Controllers. Implemented VHDL code and specification release using Perforce revision control and release document tools.

Confidential, Melbourne, Florida

System Verification Consultant

Responsibilities:

• Responsible for the Software Qualification and Regression testing for the verification of the RIU Unit module under the Pro Line 21 integrated avionics product line. I completed all Level A, Do 178B software testing and software integration verification. Develop C++ and Matlab code to improve test data generation.
• Generate test plans for all software modification and LabView TestStand test VI. I ran all regression testing on RIU unit software releases. Provided code and documentation review for software releases. Lead project for test setup and test verification for reliable department on the Cats21 Test Station.
• Set up project and test bench environment directory. Implemented ECO code and specification release using Clear Case revision control and Clear Quest for ECO tracking and DOORS requirements tools.

Confidential, Melbourne, Florida

Design Consultant

Responsibilities:

• Responsible for the Tool Qualification Plan for ModelSim Simulator, Code coverage and Actel SmartTime Static Timing Tool under the Do 254 specifications for Target Device: Actel ProASIC+ APA600. I completed VHDL code verification of an ACTEL ProASIC+ APA600, MPIO Multi- channel standard serial I/O FPGA. MPIO provides the configuration and control of multiple I/O channels, including ARINC-429 (8 TX; 8 RX), ARINC-453 (2 RX), RS232 (2 CH) RS422 (4CH), CANBUS, SATCOM, STEC-55 autopilot annunciator, and discrete input for LVTTL, LVDS, SSTL I/O on the Multi-Purpose I/O III card (MPIO3).
• I assisted in the generation of traceability for FPGA system level requirement for product and design. Also facilitate communication interface with the card's MC9S12 Bytefligh communications processor. Ran design simulation of these designs to generate testbench for functional simulation. Set up project and test bench environment directory. I implemented C++, VHDL code, PDR, CDR, BOM and project specification release using Perforce revision control, Omnify release document tools and DOORS requirements tools.

Confidential, Orlando, Florida

Design Consultant

Responsibilities:

• Responsible for the design modification of a Xilinx CPLD for SPI type interface to TxRx Tranreceiver. I completed VHDL code verification testing and hardware debug of a Xilinx Cool Runner XRC3128XL-6VQ100 CPLD. I have designed a FPGA interface data controller for a XR4VLX25SF363 FPGA.
• Develop C++ and VHDL code to improve test data generation. Completed design simulation and verification of these designs and the board BOM. I was accountable for board startup testing for LVTTL, LVDS, SSTL and bus interfaces. Generation test bench development as well as hardware debug for both Xilinx parts for the Radar Sensor product. Set up project and test bench environment directory. I have implemented VHDL code and project retention repository using Source Safe revision control tools.

Confidential, Grand Rapids, Michigan

Responsibilities:

• Responsible for providing verification methodology consulting for a CPU's Airborne flight computer ASIC design. This Airborne design is based on the IBM PowerPC 750GX microprocessor. I was accountable for generating VHDL test cases based on the design requirements for ASIC design verification under the Do 254 specification.
• Lead designer in providing VHDL code generation for multilevel CPU ASIC design based on a Risk Processor. Generated test code to verify CPU design interfaces such as DMA, DDR, UART, I2C, SDRAM, Aux Bus, PCI, 60x bus review test input for LVTTL, LVDS, SSTL interfaces.
• I have generated VHDL and C++ code to create verification environment for internal and external DUT subsystem verification. I developed C++ and VHDL for IC2 RTL to isolate clock skew design problems. I generate of traceability system level requirement for product and design in DOORS. Set up testbench environment directory and code repository using CVS revision control tools.

Confidential, Largo, Florida

Responsibilities:

• Responsible for providing UVM/RVM verification methodology consulting for a three ASIC Aerospace chip design. Generated chip level testbench for AMBA multi interface ASIC. I generated Verisity Specman E code test files to support AHB to SpaceWire, Rapid IO and Firewire and Jbus protocol test bench verification. I developed C++ and VHDL to interface test blocks to eVC’s improve test interface.
• I completed review of eVC’s packages e code to verify ERM compliant. Set up testbench environment directory using CVS revision control tool. Generate UVM design interface to verify SystemVerilog and Verilog models in system level Testbench.
• Reviewed verification design flow and regression test suit to customize verification environment for a multi protocol design in the UVM methodology. Generate customize ecode test cases to verity multi-interfaces protocol design over AHB bus. I completed the task of E code PDR, CDR reviews and software tool installs.

Confidential, Ocala, Florida

Responsibilities:

• Responsible for providing verification methodology consulting. I completed the task of generating a Vera socket interface within a testbench to support Vera and RVM to C code simulation usability. Developed C++, TCL and VHDL for IC2 RTL to isolate clock skew design problems set up testbench environment directory using Perforce revision control tools.
• Develop prototype interface verification environments for legacy C code model hardware testing. I have provided technical training on Vera Socket and VSV Verification Methodology. Reviewed verification design flow and regression test suit to customize verification environment.

Confidential, Orlando, Florida

Design Application Engineer

Responsibilities:

• Responsible for generating Product and Customer Support for, Propriety IO controller. Team leader and manager for project development from start to completion. I designed product documentation and data IO flow control for VHDL code for the FPGA hardware design.
• Reviewed and tests inputs for LVTTL, LVDS, SSTL and bus interfaces. Responsible for FPGA design level verification flows and functional simulation debug. Generated ATPG and DFT design verification goal and tracked all generated Eco's and the review of PDR and CDR.

Confidential, Durham, NC

Consulting Software Application Engineer

Responsibilities:

• Responsible for providing verification methodology consulting and technology product support. I provided tech support for East Cost customer using Remedy support tool.
• Develop prototype RVM verification environments for customers using Specman, Verilog and VHDL. I provided technical training on Specman and

Confidential

Verification Engineer

Responsibilities:

• Responsible for providing Life Cycle Design Methodology and Verification Methodology for ASIC Design Department for Technology Product Design. Responsible for the generation of a verification design specification document. Define verification flow and regression test suit.
• I generated Perl scripts to automate regression test suit functions. Generated dataflow block models that manage data structures of test vectors. I wrote system verification test procedures for top-level DFT and ATPG testing for video and voice network processor as well as PDR, CDR reviews.

Confidential, Research Triangle Park, NC

Verification Engineer

Responsibilities:

• Responsible for defining verification and test approaches for full system level critical dataflow for Transport Physical Communication layer. Generated dataflow block models to manage data structures. Data list structures where used for buffer management and buffer manipulation of frame data fields.
• Dataflow Directives of the Network Processor functional procedures where coded to test, functional directives for BCB, FCB and CAB Pools and Frame Processing testing. Wrote VHDL data structure to functional implement operation of the Dataflow Directives.
• Define the interface protocol for Frame Processing block. Write system acceptance test procedures to generated Data Pool record lock model that would successful integrated into full level testing. I completed simulation of all function directives using ModelSim simulation tools and complete all specification required for PDR and CDR reviews.

Confidential, South Portland, ME

Design Engineer

Responsibilities:

• Responsible for the design and simulate RTL for a CMOS/BiCMOS high performance Interface products. Completed all design requirements using Cadence simulation tools to support design Characterization/Validation for design product.
• I completed simulation of all function directives using simulation tools and complete all functional specification directives for PDR and CDR reviews. Oversee Layout work, including physical verification.

Confidential, Austin, TX

Verification Engineer

Responsibilities:

• Responsible for the integration of 219x peripherals Agents blocks into top-level test environment. Verify Agents functional usage under the ABEL Simulation Environment for new high performance DSP. Responsible for Agents test methodology and measuring test coverage development.
• Generate Perl scripts to automate design simulation and verification of both block and RTL levels. Generated Verilog code to fix or modify test bench for simulation RTL and block level verification.
• I completed verification of all function directives using simulation tools and complete all functional specification directives for PDR and CDR reviews.
• Reviews and evaluates test requirements.
• Executes comprehensive test plans, procedures and schedules supporting production and development programs.
• Performs data review and data reduction and generates final reports.
• In addition, provide troubleshooting leadership, identify cause and corrective action in order to solve technical production problems.
• Strong oral communication skills needed.