Sr Principal Engineer Resume San Jose, CA - Hire IT People

SUMMARY

Experienced (15+ years) RTL (Digital Design) engineer, Team Leader. Mentor.
Strive to create clean, concise and well documented designs.
Self motivated and high emphasis on quick resolution of internal and external customer issues.
Always interested in exploring new areas to expand my knowledge.

TECHNICAL SKILLS

SystemVerilog
Verilog
VCS
Perl svn git
VMM
C
C++
Spyglass Lint
Synthesis
Timing Analysis

PROFESSIONAL EXPERIENCE

Confidential, San Jose, CA

Sr Principal Engineer

Responsibilities:

Micro - architecture and RTL coding of blocks in multi-port high speed Gigabit Ethernet ASICs (10/40/100 Gbps Converged Ethernet Adapters)
Rx side RDMA (RoCE) protocol processing engine (Infiniband Transport Layer). Packet validation, retransmission requests and context update are performed at a high packet rate using a multi-threaded, pipelined processing engine. Created and presented the micro-architecure to the extended team.
Ethernet packet parsing and filtering (MAC, VLAN, Ipv4/Ipv6, TCP, UDP, FCoE, RoCE, GRE, VXLAN). VEPA (IEEE 802.1qbg) and VEB switching. Hardware assist for MAC/VLAN/IP/TCP Connection filtering, RSS routing, CRC/checksum validation, Pause Buffer Size Calculations for flow control. De-mux and Re-order packets across multiple datapaths - define worst case traffic patterns for buffer size calculation. Receive Statistics. Micro-architecture documentation.
Traffic Shaping per the IEEE 802.1az specification (ETS). The design allows strict priority, work-conserving and max-bandwidth traffic shaping based on priority-groups.
Ran spyglass lint. Perform synthesis and timing, fanout and other backend fixes.
Worked closely with multi-site Verification, FPGA, Firmware, Driver teams.
Customer interface: Represent ASIC team in customer site visits. Understand customer requirements and work with firmware/driver teams to enable solutions on existing products.
Mentor for junior engineers. Recruited and mentored interns as part of the company's Summer and Winter Intern programs. Enabled them to effectively contribute to on-going projects.
SystemVerilog/VMM: Created SystemVerilog/VMM testbench, Packet Generator, Packet Parser. Verified packet parsing and filtering module via fully random testing. Used advanced VMM concepts like the Multi-Stream Scenario Generator.
Scripting (Perl, bash, emacs lisp, makefiles) and object oriented programming. Effective at automation of repetitive tasks; written 1000+ lines for some perl scripts having advanced data structures.

Confidential, Milpitas, CA

Team Lead

Responsibilities:

Main responsibility included leading a team of 9 verification engineers, contractors and interns. The deliverable was a flash controller IP going into Confidential 's flash cards (USB, Compact Flash, SD cards, Memory Stick). Responsible for testplan creation and signing off on verification in a schedule driven, fast-paced environment, based on testplan and code coverage. Interfaced with Project Managers to provide schedule updates.
Miscellaneous: * Script to compile and run simulations (Perl and Makefiles). * RTL coding for Auto-calibration logic to calibrate delay lines to PLL clocks.

Confidential, Longmont, CO

Member of Technical Staff (MTS)

Responsibilities:

Top level clock muxing and reset synchronization. Clock dividers. Shutting down clocks based on power management events.
Verification of a Display Controller. Responsible for the C++ reference model, transactors and testplan. The Display Controller is responsible for transferring framebuffer contents to an external display device (CRT).
Custom SRAM design: Designed custom SRAMs. Special purpose bitcells (single and dual port).
Miscellaneous: * Implemented March-B BIST algorithm in verilog. * An analog hardware Random Number Generator that was proven on Silicon. * A memory compiler in C++, to create HSPICE, Synopsys Liberty, GDSII layout views of memories based on an input config file. * A memory characterization tool in Perl.

Confidential, Cincinnati, OH

Graduate/Research Assistant

Responsibilities:

Graduate Assistant: Unix systems administration, web pages design, search engine design, print quota software design and implementation, systems security and firewall configuration.
Research Assistant: Evaluation of VHDL-AMS simulators based on their mixed-signal performance. (Masters Thesis)

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Sr Principal Engineer Resume

San Jose, CA

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