SUMMARY:

• One plus year of experience wif Nuclear V model HLCD for Verification and Validation and Environmental Qualification support.
• Sixteen years as a design engineer and over 6 years of EMC and EMI experience wif skillful knowledge of LabView, CST tools, pre - compliance testing according to internal test methods, performing simulations, running tests, analyzing and reporting status.
• Expert knowledge in teh Life Cycle Development SDLC, HDLC, QTP, ITAR, QTR and Verification, Validation, Design, Software.
• Over 10 years of adept experience wif of CAD / CAE tools / mentor graphics.
• Over 10 Years of Analytical approach to problem solving and POC.
• Experience in teh design of ASIC, FPGA design, simulation, VHDL, HDL, Verilog, Specman E, Vera, RVM, SystemVerilog, HVM, OVM, OVC, CDV, TLM, VMM, API, RTL level modeling, DFT and Verification: methodology requirements, Testbench generation.
• Experience in teh design and testing of EMC and EMI TEMPeffect related to teh electromagnetic phenomena on a product function operation. I applied test standards RTCA DO-160D EUROCAE ED-14D, and Mil-Std 461 E to test confirmative to teh avoidance of any interference TEMPeffects on teh correct operation of a product.
• I has design and development experience of active/passive circuits such as, filters, Transmission Lines, phase shifters, amplifiers (LNA), oscillators and mixers for RF-to-IF conversion designs.
• I has applied good oral/written communications skills, wif teh ability to analyze and resolve integration problems; demonstrate individual initiative, when working as part of a project team.
• Has skills in Project Management and teh development of products, as well as customer support .

TECHNICAL SKILLS:

Revision Control Software: ENOVA, Peer, PAACE, ClearQuest, TDM, ClearCase, Perforce, Omnify, Source Safe, RCS, Remedy, CVS and PLM.

Computer Systems: Sun, HP-UX, Apollo, DEC, VAX, IBM, Cyber 170 and PC's.

Operating Systems: UNIX, DEC Windows, Macintosh, VMS, MS Windows, MS DOS.

Navigation System: ADS-B, SATCOM, AWOS and GNSS.

Design Languages: VHDL, HDL, OVM, VMM, UVM, AVM, RVM, Verilog, Vera, E, System Verilog, VSV, SystemC, Specman, Makefiles.

Programming Languages: Perl, TCL, C/C++, and C #, SQL, Pascal, MathCAD, Radspice and Fortran.

CAE Software: MS Visual, Altium, Chip Scope, MatLab, Allegro, LabView, TestStand, ModelSim, Quartus, Code Coverage, Libero, SmartTime, Simplify, AutoCAD, FlashPro, Vera, Specman, Synopsis, PrimeTime, Visual HDL, Mentor Graphics, Concept, Cadence, V-System, NCsim, Renoir, Leonardo, OrCad, Max Plus, Synplicity, Galileo, Xilinx, Actel, Altera, VCS, Chip Express, Code Coverage, Static Timing, Omnisys, EEsof Touchstone, Libra, ICgraph, Academy, Silver- Lisco, Mainsail, Zycad, CALMA, CDC-MIDAS and Network CAD tools.

PC Software: DOORS, Slate, Microsoft Word, Excel, Powerpoint, Access, Project and Visio

Emulators: Lauterbach Trace 32Specification's Familiar wif: SAE ARP 4745A, ARP4754, IEEE 1012, 829, 7-43.2, 1149.1, RG 1.180, 1.209, EUROCAE, RTCA, Do-178B, 160, 254, ByetFlight, RS422, RS232, 485, PCI 1650, SPI, ARINC-429, 453, 461 E, 810 F, 600, 610, 615A, 615, NTSC, CANBUS, LIN, I2C, Ethernet, Rapid IO, USB, Smart Card, SPI3, AMBA, AHB, Firewire Fiber Channel, Ethernet, 802.1, 802.11,DFT, JTAG, BIST, LVTTL, LVDS, SSTL, Jbus, FEMA, CDR, PDR, MTBF, FHA, FTA, EMI and EMC.

FPGA: Xilinx -Virtex-4, Virtex-5, Actel, Altera Stratix-II XILINX ISE 10.1, Virtex- 2, 4 & Virtex - 5, Actel APA-750, Altera FLEX 10k/20k CPLD & Stratix -II -GX Devices

Microprocessor: Intel x486, 386, X86, Pentium - II & III, PowerPC-8270, 8051, 405, 440, RISC, Motorola, ARM, Texas Instruments - DSP's (C6X & C7X) and Microcontroller.

PROFESSIONAL EXPERIENCE:

Confidential, Wilmington, NC

V&V Test Engineer Consultant

Responsibilities:

• My role for one plus year was working wif Nuclear V model HLCD system level Verification and Validation. I provide Validation support for HSIS, HRS, HDD and VHDL based on function requirements Project schedule I worked as a test team member for system product validation testing. Lead project setup test, traceable, validation and documentation for test reporting. I provided test solutions on failed LRU boards to determine root failures. Verified and validates solution based on LUR testing. I completed
• Verification of firmware software testing and documentation to support SourceSafe revision control testing. Completed technical review of hardware project documents based on GEH, IEEE, NRC and other industry specifications. Lead project on teh generation of Technical Design Procedure dat outlines teh development of a methodology for testing Complex Integrated Electronic FPGA’s, CPLD’s, PLD’s and schematic updates using Allegro. I worked on generating Environmental Qualification for components and system level products. I was responsible for teh generating product Environmental Qualification Test Plans, Test Procedure, testing and scheduling equipment resources.

Confidential

V & V Engineer

Responsibilities:

• My role is responsible for Validation and Verification on A400M aircraft Floor Based Handing System product and ITAR. In dis role I'm also responsible for validation of derived system and hardware requirements, inspection, FEMA, MTBF, FHA, FTA and Validation and Verification analysis. I generated DOORS requirements, support for Validation analysis and Verification requirements tracking. Verification using DO-254 practices. Retain teh generation of Testbench generation using VHDL. Utilize teh Freescale MPC8270
• PowerPC processor device product families. Developed MPC8270 PowerPC processor for LCU top level environment dat define teh I/O pin outs to teh DUT and OVM components for SystemVerilog interface to support ModelSim SE Simulator. dis consisting of coupling all teh OVM components and teh DUT into a single top level block. Leverage block level simulation to reduce simulation schedule. Employed teh used teh Actel Libero design tools along wif Simplicity Simplify synthesis and JTAG. Apply Mentor Graphics device level design tools for functional verification of MPC8270 PowerPC processor for LCU. Applied validation and verification for C++ device test code and troubleshooting based on system level requirements and proof of concept. Review test input for LVTTL, LVDS, SSTL and bus interfaces. Task as teh intermediaries between teh tests technician and Hardware Engineering to ensure product system requirement standards are met. Responsible for all system related SAE ARP 4745A, DO-160, DO-178, DO-254, PDR, CDR, BOM, and A400M based on Germany custom EUROCAE product system requirements.

Confidential

Systems Engineer

Responsibilities:

• My role is responsible for Verification on Honeywell aircraft Flight Control product. In dis role I'm also responsible for validation of derived design hardware, inspection, and analysis of analog ATP for TVO generation. Generated MatLab simulation and mathematical models for Signal Analyzer to test analysis, proof of concept POC and verification system level requirements.
• I generated TVO test requirements for both teh ComAux and MonAux design boards. Task as teh intermediaries between teh tests technician and
• Hardware Engineering to ensure TVO requirements testing are met. Responsible for all hardware related DO-160, PDR, CDR, BOM and DO-254 product system requirements based on ARP4754.

Confidential, Phoenix, AZ

Systems Engineer

Responsibilities:

• My role is responsible for GAP Audit of VM Methodology as define in teh Life Cycle Product Develop Plan. dis audit covered teh review of all FRD FPGA Requirements
• Document, VDC Local Bus FPGA Verification Design Container, VTR FPGA Verification Test Results, VTP FPGA Verification Test Procedure, HVP Hardware Verification Plan,
• DVV Development, Verification & Validation Plan, DDD FPGA Device Design Document, PDC PLD Design Container Local Bus FPGA, HRD Hardware Requirements
• Document, VDD Local Bus FPGA Version Description Document, AID Local Bus FPGA Altered Item Drawing, and HDVP Hardware Development and Verification Plan. dis review tested VM Methodology and it implementation wifin requirement specifications. In dis role I'm also responsible for Systems Gap Audits and

Confidential

Design Verification

Responsibilities:

• Responsible for providing verification methodology consulting for a CPU's Airborne flight computer ASIC design. dis Airborne design is based on teh IBM PowerPC 750GX microprocessor. I was accountable for generating VHDL test cases based on teh design requirements for ASIC design verification under teh Do 254 specification. Lead designer in providing VHDL code generation for multilevel CPU ASIC design based on a Risk Processor. Generated test code to verify CPU design interfaces such as DMA,
• DDR, UART, I2C, SDRAM, Aux Bus, PCI, 60x bus review test input for LVTTL, LVDS, SSTL interfaces. I has generated VHDL and C++ code to create verification environment for internal and external DUT subsystem verification. I developed C++ and VHDL for IC2 RTL to isolate clock skew design problems. I generate of traceability system level requirement for product and design in DOORS. Set up testbench environment directory and code repository using CVS revision control tools.

Confidential

Design Verification

Responsibilities:

• Responsible for providing UVM/RVM verification methodology consulting for a three ASIC Aerospace chip design. Generated chip level testbench for AMBA multi interface ASIC. I generated Verisity Specman E code test files to support AHB to SpaceWire, Rapid IO and Firewire and Jbus protocol test bench verification. I developed C++ and
• VHDL to interface test blocks to eVC’s improve test interface. I completed review of eVC’s packages e code to verify ERM compliant. Set up testbench environment directory using CVS revision control tool. Generate UVM design interface to verify
• SystemVerilog and Verilog models in system level Testbench. Reviewed verification design flow and regression test suit to customize verification environment for a multi protocol design in teh UVM methodology. Generate customize ecode test cases to verity multi-interfaces protocol design over AHB bus. I completed teh task of E code PDR, CDR reviews and software tool installs.

Confidential, Ocala, Florida

Design Verification

Responsibilities:

• Responsible for providing verification methodology consulting. I completed teh task of generating a Vera socket interface wifin a testbench to support Vera and RVM to C code simulation usability. Developed C++, TCL and VHDL for IC2 RTL to isolate clock skew design problems set up testbench environment directory using Perforce revision control tools.
• Develop prototype interface verification environments for legacy C code model hardware testing. I has provided technical on Vera Socket and VSV Verification Methodology. Reviewed verification design flow and regression test suit to customize verification environment.
• Generated customize design verification environments to test Mac and Phy interfaces over AHB bus to also include PDR and CDR reviews. I completed teh task of Vera code reviews and software tool installs used to validate proof of concept for design projects.

Confidential

Design Application Engineer

• Responsible for generating Product and Customer Support for, Propriety IO controller. Team leader and manager for project development from start to completion. I designed product documentation and data IO flow control for VHDL code for teh FPGA hardware design. Reviewed and tests inputs for LVTTL, LVDS, SSTL and bus interfaces.
• Responsible for FPGA design level verification flows and functional simulation debug. Generated ATPG and DFT design verification goal and tracked all generated Eco's and teh review of PDR and CDR.

Confidential

Consulting Software Application Engineer

Responsibilities:

• Responsible for providing verification methodology consulting and technology product support. I provided tech support for East Cost customer using Remedy support tool. Develop prototype RVM verification environments for customers using Specman, Verilog and VHDL. I provided technical on Specman and
• RVM Design Verification Methodology. Reviewed verification design flow and regression test suit to customize verification environment. Generated customize design verification environments to test PCI Evc's and others standard interfaces. I completed Specman code PDR, CDR reviews and software tool installs.

Confidential

Verification Engineer

Responsibilities:

• Responsible for providing Life Cycle Design Methodology and Verification Methodology for ASIC Design Department for Technology Product Design. Responsible for teh generation of a verification design specification document. Define verification flow and regression test suit. I generated Perl scripts to automate regression test suit functions.
• Generated dataflow block models dat manage data structures of test vectors. I wrote system verification test procedures for top-level DFT and ATPG testing for video and voice network processor as well as PDR, CDR reviews.

Confidential

Verification Engineer

Responsibilities:

• Duties: Responsible for defining verification and test approaches for full system level critical dataflow for Transport Physical Communication layer. Generated dataflow block models to manage data structures. Data list structures where used for buffer management and buffer manipulation of frame data fields. Dataflow Directives of teh Network
• Processor functional procedures where coded to test, functional directives for BCB, FCB and CAB Pools and Frame Processing testing. Wrote VHDL data structure to functional implement operation of teh Dataflow Directives. Define teh interface protocol for Frame Processing block. Write system acceptance test procedures to generated
• Data Pool record lock model dat would successful integrated into full level testing. I completed simulation of all function directives using ModelSim simulation tools and complete all specification required for PDR and CDR reviews.

Confidential

Design Engineer

Responsibilities:

• Responsible for teh design and simulate RTL for a CMOS/BiCMOS high performance Interface products. Completed all design requirements using Cadence simulation tools to support design
• Characterization/Validation for design product. I completed simulation of all function directives using simulation tools and complete all functional specification directives for PDR and CDR reviews. Oversee Layout work, including physical verification.

Confidential, Austin, TX

Verification Engineer

Responsibilities:

• Responsible for teh integration of 219x peripherals Agents blocks into top-level test environment. Verify Agents functional usage under teh ABEL Simulation Environment for new high performance DSP.
• Responsible for Agents test methodology and measuring test coverage development. Generate Perl scripts to automate design simulation and verification of both block and RTL levels. Generated Verilog code to fix or modify test bench for simulation RTL and block level verification. I completed verification of all function directives using simulation tools and complete all functional specification directives for PDR and CDR reviews.
• Reviews and evaluates test requirements.
• Executes comprehensive test plans, procedures and schedules supporting production and development programs.
• Performs data review and data reduction and generates final reports.
• In addition, provide troubleshooting leadership, identify cause and corrective action in order to solve technical production problems.
• Strong oral communication skills needed.
• Candidate must be an excellent technical writer (job entails writing test procedures (Acceptance Test and Qualification Test and reports) and be proficient wif Microsoft Word and Excel Required Skills / Qualifications: