CAREER OBJECTIVES: Design, Develop or Verify SoC's, ASIC's, FPGA's and embedded hardware systems

Project, program and product development management
SoC, ASIC & EDA

EXPERIENCE:

Hands-on experience with SoC/ASIC/FPGA Architecture, Design & Verification,
ARM AXI/AHB/APB SoC, CoreAssembler, DesignWare, Design Compiler/Analyzer Synthesis, Timing Constraint generation & STA,
Primetime STA, Verilog/VHDL, Distributed Makefiles for Simulation and
Synthesis builds, PERL, shell scripting, Tcl, VCS, Modelsim, NCsim, Synplicity,
Covermeter, Quartus/Altera, Xilinx, Chipscope, Lattice, Vera, Specman, SystemVerilog/SVA, C/C++, OVM, AES Rijndael encryption, decryption and key generation, Unix, Linux, AIX, Debussy, Functional, Line, and Conditional Coverage Metrics & Test Optimization, LSF batching, Assembler programming

WORK EXPERIENCE:

ARM & 68K SoC Architecture & Design, etc.

1/07 to Present Confidential,Austin, TX
Sr. SoC/ASIC/FPGA Design and Verification Engineer
SoC/ASIC/FPGA Design and Verification services, feasibility studies, patent work

• Designed directed tests for ARM9 based multi-processor broadband multimedia SoC - Ran regressions using NCSim, C, TCL, Make and PERL - NDA
• Built architecture for ARM AXI/AHB/APB SoC, w/ CoreAssembler and DesignWare blocks - AMBA/OCP/Spearhead SoC - for Motorola
• FPGA Pre-silicon verification of subsystem blocks using scripted synthesis with Quartus, Synplicity, Perl, C++, Linux - Verified on hardware platform - Motorola
• Architected, wrote and synthesized VHDL for a large custom FPGA video design including SERDES, FIFO's and many other custom video engine blocks - NDA
• Stitched Verilog IP blocks together by customizing interfaces & compiled into a SystemVerilog environment - Xilinx Chipscope Pro core generator & inserter (ICON, ILA, ATC2, etc.) - for Intel
• Designed & simulated Blackfin interface, A/D acquisition control, and custom fifo for target Xilinx Spartan3 FPGA in Verilog, compiled w/ Synplicity - NDA
• Researched Nand flash controller architectures for a Verilog design and feasibility study, wrote NTSC video encoder verification plan - for Pinpoint Solutions
• Environmental Engineer for Air Emission Standards modeling - for TCEQ

7/06 to 1/07 Confidential,Austin, TX (Contract)
Sr. FPGA Design and Verification Engineer
Encryption and Decryption engines for Military flight recorder

• Researched and purchased AES Rijndael encryption, decryption and key Generator Verilog IP blocks after exhaustive vendor feature comparisons (functionality/algorithm, speed, area, etc.)
• Built system into Xilinx Virtex FPGA, synthesized, met timing constraints, and ran encryption/decryption simulations on data streams to verify functionality

1/06 to 7/06 Confidential, NC (Contract)
uP L2 Cache Design Verification Engineer
Cell Phone SoC/ASIC Microprocessors

• L2 Cache Coherency Verification in an ARM uP Core environment
• Wrote Boundary and Stall Condition Directed Tests for the L2 Cache in a native CPU Model language, w/ Bus Model Delay commands & Memory Model formatting/fill with self verify of returned data
• Composed thousands of lines of PERL to auto-generate these Tests and Memory Files in the Unix, SystemVerilog(SVA) environment
• Ran Simulations using these generated test files in the CPU Model and L2 Verilog environment and analyzed output waveform results within that CPU Model, L2 and Testbench using Debussy to verify correct operation of the L2 Cache

5/05 to 12/05 Confidential,Austin, TX (Contract)
Sr. Design and Verification Engineer
Digital FPGA and uP Embedded Systems

• Design, Integration(Synthesis) and Verification of Altera Cyclone FPGA's for a 64 Bit Medical Bidirectional Video Mux/FIFO Application - Synplicity & C/C++
• Design of 80186 Motherboard System w/ Multiple FPGA Designs Replacing obsolete parts on a Legacy Design for a Military Contractor

1/05 to 5/05 Confidential,Austin, TX (Contract)
Sr. Research and Development Engineer
eSeries Blade Servers/ eServer systems

• Design review of new server design - Dual PowerPC, Hypertransport, Northbridge & Southbridge(Super I/O) chips, PCI-X - Temperature throttling
• Many Linux installs and blade server maintenance, bring-up and testing

6/04 to 1/05 Confidential,Austin, TX (Contract)
Sr. RTL Design Engineer
Hardware Accelerated Database Search Engines

• Wrote Verilog IP for Stratix Altera FPGA Project
• Built and ran Modelsim simulations on DDR and PCI-X bus IP blocks
• Wrote Verilog DMA interface engine to PCI-X IP block
• Participated in PowerPC based Gigabit PHY board design

9/03 to 6/04 Confidential,Austin, TX (Contract)
Sr. Design and Verification Engineer

• Developed SoC RTL Coverage Methodology
• Ran VCS/Covermeter tools and analyzed Code Coverage reports
• Investigated Verilog RTL coverage voids and recommended Test Patterns
• Used Debussy to trace signals through Design and Vera testbenches
• Wrote Scenario based Random and Directed self checking VERA testbenches
• Used Clearcase and CVS for revision control and LSF for batch execution
• Achieved 98% line and 97% conditional test coverage

11/01 to 9/03 Confidential,Austin, TX (Contract)
Sr. Design and Verification Engineer

• Built a Verification environment for four FPGA's using Modelsim
• Re-designed all VHDL modules to include reset and timing balanced clocks
• Implemented pin slew rates and floorplan pin locks in the source code
• Re-designed FPGA RTL with external system signal integrity in mind
• Built Verification suites with ASIC like Multi-clock testbenches
• Participated in the Architecture Definition of the new product electronics
• Some simple analog design/mixed signal product upgrades - DSP
• Studied and helped design w/ TI's DLP mirror cinema design technology
• Ran daily Synthesis runs w/ pin and Timing Constraints
• Consulted for high speed board design & laboratory validation - C/C++

3/01 to 11/01 Confidential,Austin, TX

• Led Architecture and Design effort for a new ARM based RISC MPEG4 video DSP chip mixed signal design including bus and memory performance studies
• Completed a full chip ARM920 Verification/Regression suite for another existing SoC design project using both NCSim & Modelsim Simulators
• Designed many Full Chip and Block Design Compiler/Vision Synthesis scripts with DFT and scan insertion including static timing analysis
• Created and maintained large Makefile systems for regenerating both the Verification/Simulation compiled libraries and Synthesis build environments after design modifications by the team with revision control
• Created new IP Block, Multi-Block and Testbench designs using Verilog, VHDL and Mentor's Renoir/HDS automated SoC block design system
• Directed custom I/O cell development for T18 UMC library using Hspice
• Managed a team and worked within it doing a many language Verification environment development - Perl, TCL, Verilog, VHDL, C-shell scripts, UNIX, Makefiles, C/C++, VSS, CVS, etc.
• Used Clearcase and CVS for revision control
• Put in charge of the Maverick EP9311 & EP9312 redesign projects w/ ARM
• Evaluated Verisity Specman and wrote tests in "e" language for several design modules
• Consulted in Pre-silicon emulation FPGA Design and SoC Validation effort
• Managed Unix installation support for trial licenses - Chronology/Specman

7/97 to 3/01 Confidential,Austin, TX

• Commissioned to evaluate current tool methodology & SoC/ASIC design flow
• Helped Architect latest cell based SoC w/ ARM vs. Coldfire or PowerPC core
• ARM7TDMI & ARM946ES new design architecture definition
• Composed many module and cluster Design Compiler synthesis scripts with DFT and scan insertion and PVT optimizations
• Led new Floorplanning Methodology discovery w/ TeraForm & Synopsys Physical Compiler tools meeting chip area constraints
• Introduced Synopsys VCS & Cadence VerilogXL simulators to younger Engineers
• Had extensive formal training in Synopsys ASIC tools - (see Education below)
• Wrote Testbenches using the new Synopsys VERA language
• Wrote Testbenches using the new Chronology Quickbench/RAVE language
• Wrote Primetime TCL scripts for design static timing analysis
• Used Clearcase and CVS for revision control
• Wrote Perl & C-shell scripts for design automation
• SoC/ASIC System level modeling with new Cadence VCC (Cierto) tool - C/C++
• Power consumption analysis in the VHDL code using Sente's Wattwatcher
• Installation, Setup, and Maintenance of tools in UNIX - System Administration
• Design timing analysis using Primetime & TCL scripting w/ multiple libraries
• Performed Cell Library timing performance evaluations w/ Design Compiler
• Debugged Cell Library model timing errors using SED/AWK & VCS/Ultima/Undertow simulators
• Evaluated Cadence PKS & Magma compilers on several design modules
• Designed and wrote TCP/IP and SDRAM Controller modules in Verilog
• Debugged Synopsys technology file errors w/ Modelsim and NCsim simulators
• Studied JTAG insertion methodologies - State machine and cells
• Repaired Artisan .18um library cell models using Verilog and simulators
• Attended system level Verification training with Mentor's Seamless
• Managed the embedded Hardware Design Team - First year, PowerPC etc.
• Created USB Hub, Smartcard, Pager & Interactive Television reference designs
• Consulted for part of the new Sony Playstation II Reference Platform

9/96 to 7/97 Confidential,Vernon Hills, IL
Sr. Electrical Engineer
Direct Transfer and Thermal Transfer Printers

• Led a new embedded uP Label Printer design for 40K/yr production
• Designed VHDL into an Altera EPLD for extended uP memory control
• Designed MC68331 Flash memory board for 10K/yr production
• Wireless chipset 802.11 LAN portable design - Matlab

2/96 to 9/96 Confidential,Waukesha, WI (Contract)
Research and Development Engineer
Magnetic Resonance Imaging Systems (MRI)

• Led new Gradient Driver RISC/DSP subsystem design for 1000/yr production
• Combined 23 Altera EPLDs into 4 custom Altera FPGAs (16-32,000 gates)
• Redesigned analog and digital combination of 13 boards into one new Gradient Driver subsystem - Huge DSP system design
• A to D conversion - mixed signal DSP, low noise analog - D to A conversion all under FPGA and Processor control - TMS320C31
• Embedded TI DSP Processor with Flash, RAM, Fiber Optics, DUART, PLL, VCXO, w/ all associated decoding done in FPGAs w/ VHDL
• Reduced the parts cost of a GE MRI machine by $30,000
• Composed 53 pages of schematic w/ Mentor Graphics

4/95 to 2/96 Confidential,Barrington, IL (Contract)
Research and Development Engineer
Linear and Focal Plane Array Cameras

• Completed six full Xilinx FPGA designs using Mentor Graphics - XC4000 digital simulator and Neocad router (10-20,000 Gates)
• "C" language software development for video acquisition system
• Pioneered & developed compile/netlisting and floorplanning/routing strategies for, at this time, the largest FPGA's of their kind
• Designed Automatic Exposure Control (Histogram) function into an existing data formatter FPGA w/schematic & XBLOX
• Implemented Pixel Decimator (Thumbnail) function in a Xilinx FPGA w/schematic & XBLOX for cockpit video
• Sun workstation system administration

10/93 to 4/95 Confidential,Round Lake, IL
Principal Engineer
Software Controlled Medication Dispensing Machines

• Managed hardware development for 11 large electronic products
• Introduced six new infrared sensor PCB's into 12K/yr production
• Redesigned UPS power supply, interface board & motherboard
• Achieved six large UL product approvals
• Existing product improvements - electrical & mechanical
• Managed Engineers, wrote design specifications & test plans

11/92 to 10/93 Confidential,Elgin, IL (Contract)
Research and Development Engineer
Microprocessor Based Cooking Controls

• Spearheaded use of new Cadence Analog Workbench
• analog design simulator for a new product design circuit topology
• Introduced VFD oven timer for 100K/yr volume to Whirlpool, Italy
• Hardware and software design - Assembly language coding
• Investigated and improved power supply topologies for new designs

EDUCATION:
Synopsys, Vera, Physical Compiler, Power Compiler, Chip Architect, Primetime I & II, Covermeter, VCS, Verilog Coding Styles for Synthesis, Advanced Design Compiler/Analyzer, Design Compiler/Analyzer, FlexRoute, Advanced Verilog,

ARM, SoC Architecture and Core use training
Mentor, Seamless Co-Sim and Renoir/HDS,
Cadence, NCsim and VCC(Cierto) modeling
Innoveda, VisualHDL
Tera Systems, TeraForm SoC/ASIC Floorplanner
Sente, WattWatcher and WattSmith Standard Cell based SoC/ASIC design using Synthesizable Verilog and Synopsys
Engineering Quality by Design