OBJECTIVE Senior Software Professional with more than eleven years experience seeks a challenging full time position in software design, development and research.
Confidential (April 2011 - present) Member of Consulting Staff Virtual System Platform group
The Cadence Virtual System Platform, consisting of the functional capabilities of the System Creator and its associated Software Developer, provides an open system-on-chip (SoC) design and analysis environment based on the TLM 2.0 and SystemC industry standards. This environment is targeted at two sets of users:
- Virtual prototype creators
Create, debug, and test individual TLM blocks, assemble the blocks into a virtual prototype (VP). Perform debugging and analysis to assure that system-level requirements are met. Use the virtual prototypes to enable early development of embedded software, or to refine the architecture of the system. The created virtual prototype is packaged for use by embedded software developers who require a "programmer's view" level of detail of its hardware components.
- Embedded software developers
Unpack, run the received virtual prototype. Load the embedded software image into memory. Test and debug the functionality of the embedded software.
Working on developing an embedded software debugging tool that interprets dwarf data and has the ability to set source/instruction breakpoints.
Language/Tools: C++, C, STL, Boost
Confidential, Inc. (September 2000 - April 2011) Senior Research and Development Engineer II, Confidential, Durham, NC (September 2007 - April 2011)
Member of the Language group within the IC Validator group. The language group is responsible for developing and enhancing a c-style language called Primeyield eXtensible Language or PXL. ICV is a comprehensive tool suite for design-yield analysis. It enables automated correction of manufacturing problems early in the design process.
- Implemented compiler optimizations for the PXL language:
- ValueNumbering based command merge optimization to merge function calls whose arguments meet certain merge criteria
- Remove Duplicates optimization to remove duplicate function calls
- Worked on different compile time performance and memory problems of PXL
- Developed a Gdb style debugger for the PXL language for ICV in C++.The debugger has all features similar to gdb and can be used to interactively run a Pxl runset on ICV.
- Developed a Tcl to Pxl generator for ICV. This provides users with a Tcl interface to ICV. It also allows users to run their Tcl script interactively on the Pxl debugger
- Working on generating lua runsets from the PXL AST for specific PXL functions to improve runtime Performance
- Working on re-writing the parser code to conform to a SSA based representation, in particular,
- Global variables
- Function inlining
- Remove duplicates
Language/Tools: C++, C, Lex, Yacc, Tcl, Lua, antlr, STL, Boost
Senior Research and Development Engineer II, Confidential, Mountainview, CA (September 2000 - September 2007)
Involved in the development of the software compiler/simulator VCS. VCS is a comprehensive verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC.
- PLI based debugger implementation for VCS
Developed a procedural interface debugger using C++, known as the Programming Language Interface (PLI) for VCS. This provides a means for verilog HDL users to access and modify data in an instantiated verilog HDL data structure dynamically. Implemented a debugging environment for VCS users, using all the three generations of verilog PLI, namely, task/function routines, access routines (Acc), and verilog procedural interface (VPI) routines.
Language/Tools: C++, C, Verilog, SystemVerilog
- Functionality extension of the debugger
Enhanced the VPI, ACC and direct kernel interface (DKI) functionality in the VCS debugger to support SystemVerilog datatypes and constructs. This enabled both verilog and Sytemverilog users to debug in VCS.
Language/Tools: C++, C, Verilog, SystemVerilog
- Standard Delay format (SDF) annotation for mixed verilog-VHDL designs
SDF files contain timing values for specify path delays, timing check constraints, and interconnect delays. The SDF annotator is a tool to back annotate SDF data to the verilog simulator. Designed and developed the SDF annotator for mixed signal designs.
Language/Tools: C++, C, Verilog, VHDL
Senior Research and Development Engineer I, Mountainview, CA Designed and implemented multiple features in VCS. This includes:
- Debug support in VCS for fully and partially encrypted verilog and VHDL designs
- Multiple timescale related system tasks in verilog
- DDG generation of generate blocks and other verilog constructs
- 2-state to 4-state conversions for signed entities for systemverilog datatypes
- Parser support for different verilog constructs
- Value change dump for systemverilog constructs
- Cumulative PLILearn support
Language/Tools: C++, C, Verilog, SystemVerilog, Lex, Yacc
Research and Development Engineer, Marlboro, MA
- Implementation of verilog 2000 features
- VCS coverage project
- VCS Infrastructure
Language/Tools: C++, C, Perl, Verilog
Confidential (August 1998 - September 2000)
Graduate Research Assistant Department of Computer Science
- Developed a translator from ODBC to OQL (M.S. Thesis).
- Development of a translator from Nemeth Math Braille to LaTeX
- Design and development of Java based software packages.
Language/Tools: Java 2 (AWT, JDK, Swing), Symantec Visual Cafe, NetBeans Developer.
Graduate Teaching Assistant Department of Computer Science
Designed and graded assignments and laboratory tutorials. Language/Tools: C++/C, Shell Script, Visual Basic.
EDUCATION M.S., Computer Science, M.Sc., Mathematics B.Sc. in Mathematics