- Twenty plus years design experience in digital design including ASICs, FPGAs, and PCBs.
- Software development for embedded Confidential and for test tools.
- Strong integration and debugging skills.
- Project leadership including architecture development, leading cross functional teams, managing sub - contractor technical development, coordinating integration activities.
- CAS from the Confidential School of Engineering Management.
- Scheduling and tracking, CAM EVM certified.
- Proposal experience including both technical and cost.
- Strong written and oral communications skills. Windows, and MS Office, Visio, Project.
- Proficient in Confidential, Verilog & C. Competent in MATLAB, C++, Assembly Code & DOORS
Confidential, Norwich, NY
- Lead engineer for iScan2 Flame Scanner. Develop TMS320 Confidential based hardware and software to detect presence of flame for safety critical operation of industrial burners. Research and development of Confidential algorithms to evaluate optical data.
- Use Mentor Graphics PADS board development tool set and TI Code Composer Studio for software development.
- Develop Confidential (automated test equipment) using LabWindows C based programming to verify product functionality and support research and development.
- Support production at off-site vendors. Coordinate product enhancements for producibility.
Engineer, North Confidential, NY
- Hardware Lead for Confidential radar. Resolve complex technical issues in support of production. Take active role in developing hardware to mitigate obsolescence. Port existing Confidential onto new hardware incorporating enhancements. Simulate using Active Confidential . Implement Confidential designs using Synplicity and Confidential ISE. Perform system integration and validation.
- Sub-array beamformer design lead for OWL program. Lead multi-discipline team developing state of sub-assembly for experimental radar system. Designed PCB with Ethernet Switch and critical timing signal distribution. Designed digital portion of RF beamformer PCB. Schematic capture using Dx Designer.
- Developed flexible BIT architecture for widely used ECM hardware. Testing includes off-line invasive tests and on-line tests. Performance of communications paths, environmental conditions and VSWR checks.
- Integrated Product Team Lead for Confidential OBE Canister. Lead multi-disciplinary multi-site team that developed data concentrator to converted 15 data sources into single 10 Gig Ethernet optical link. Had complete design responsibility including architecture, overseeing schedule, risk management, budget, EV reporting, integration, and formal design sell off.
- As Lead Hardware Engineer ensure engineering processes are followed, participated in design concept and cost estimating in support of new business, created and presented Cost Sign-off packages for Equipment Engineering, using GRID coordinate staff with functional managers.
- As the Lead Hardware Engineer and Lead Digital Engineer in the Acoustic Sensors group have participated in proposals for MFTA, RAP/VLA and Confidential . Played a instrumental role in both Tech and Cost Volumes on Confidential . Played significant role in developing the IMS and EV planning, track progress as well as risks and opportunities in ROADS for MFTA.
- Lead effort to drive the LAB/LVA Network Interface Card validation and integration effort. Identified needed resources, coordinated multiple disciplines, set team priorities and lent a hand developing STE sync card.
- As the Lead Digital Engineer in the Acoustic Sensors group have participated in proposals for LVA, SAES, S80 OBE and NextGen TB-34 in the capacity of technical, cost, schedule and risk assessment. Have developed and tracked detailed project schedules. Schedule work assignments for four digital engineers and provide By the Name Plan input for future needs.
- For the Confidential program, developed a parameterizable and flexible architecture for the Network Interface Card. With a goal of multiple re-use, this architecture supports current telemetry interfaces as well as future Ethernet implementations. Architected GigE Optical interface for use on LAB and LVA using an embedded PowerPC in a Confidential FPGA. Have assisted several additional programs, such as ARTIST, by developing blocks of Confidential code and assisted less experienced digital engineers with Confidential and board design needs.
- Architected, Coded and Verified the Confidential for the RADAR Controller Interface in the AHE Transmitter. Wrote Confidential Code and self checking testbench also in Confidential, for easy regression testing, to simulate design in ModelSim. Design features include Serial FPDP, message partitioning and building, UART interface, several I2C interface sensors and PMFL features including safety requirements. Participated in Design Verification Testing.
- Designed synchronization source for a SONAR in an Altera Confidential on a PCI COTs board.
Engineer, Boise, ID
- As part of a team, developed two generations of a pipelined image processing Confidential with an embedded ARM processor for MFP (multi-functional products, printer/scanner/fax) products. The first generation was 133 MHz with 2.7 million gates and the second was 167 MHz with 6 million gates. Worked on design from conceptual stage through proto-type verification.
- Wrote Confidential in Verilog, modified existing Confidential code, and synthesized in Design Analyzer. Blocks designed include front-end interface with pipeline pacing circuitry, embedded LUTs, Confidential interface, horizontal and vertical scaling, and updates to existing LSB and PCI designs.
- Validated design in Modelsim using VERA and Seamless tools. Used PERL for scripts.
- US Patent 7457459 for Monochrome and Color Transfer in a Multi-Function Product.
Engineer, Rochester, NY
- Designed and verified a synthesizable Confidential IP Core for the CAN Bus Interface.
- Performed Confidential and Verilog logic designs of up to 125MHz per customer specs in Confidential Spartan and Virtex Confidential . Used Synplicity and Confidential for synthesis and Confidential Foundation for place and route. Validated designs with Verilog test benches using ModelSim.
- Converted ASICs to Confidential, multiple Confidential to single device, Altera Confidential to Confidential .
- Verified Confidential timing with Primetime and functional equivalence with Formality.
Engineer, Rochester, NY
- Designed and integrated crypto communication products using Motorola 68331, PC860.
- Digital logic design in 4000 Series Confidential using M1 Software.
- Analog design including power supply, A to D, D to A, and linear circuits.
Engineer, Denver, CO
- Developed sub-system digital interface and control architecture.
- Designed digital PC boards using programmable logic.
- FPGA/ Confidential design using Visual Confidential based tool).