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Asic Design Intern Resume


  • Looking for challenging opportunity in the field of FPGA/VLSI Designing and verification (Backend designer) and Digital System Design where my skill sets help me grow and expand the company.


Language: VHDL, Verilog, System Verilog, SystemC, Perl

EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx - vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice, SQL.

Coursework: Introduction to CMOS Designing Introduction to Microcontroller and Microprocessor VLSI Design Principles FPGA Designing with VHDL Image Processing Digital Logic Design Digital Design with FPGA Mixed Signal IC Design Analog IC designing


ASIC Design Intern



  • Assist senior engineers in the architecture and design of the ASICs using latest process technologies and CAD tools and responsible for developing micro architecture module with the help of architecture staff.
  • Play active role in chip integration and flow development, processor design and memory subsystem design
  • Responsible for providing support to physical design and product engineering staff in high volume production.

VLSI Design Intern



  • Designed and developed electronic components.
  • Performed unit level validation environment development, design schematic capture, floor planning, test plan, routing, and logic equivalency, circuit simulation, timing closure and test case implementation for the verification of design blocks
  • Implemented logic complex design blocks using RTL coding.
  • Executed the chip enhancement procedures including the procedures related to synthesis and time investigation.
  • Purpose of this project was to design and implement VGA Controller on FPGA.
  • The VGA Controller program is written based on the block diagram using Verilog HDL.

Tools Used: Nexys2 Digilent FPGA board, Xilinx Vivado.




  • Implemented a 6T SRAM to overcome power consumption and a transient voltage boost on the word line to improve the write performance.
  • 6T SRAM architecture is chosen for memory bit cell and an array is designed with that bit cell. Transient and parametric analyses were carried out in the simulation process and the power consumption is estimated.

Tools used: Layout editor, Cadence Virtuoso schematic editor, Hspice.




  • Designed a layout to perform 4:16 decode operation.
  • Both layout and schematic circuit of the Confidential underwent DRC and then simulated through LVS to ensure they were identical. Results of the layout and schematic circuit were essentially identical and matched the theoretical results.
  • Traffic Light sequence is generated using a specific switching mechanism which will help to control a traffic light system on a road in a specified sequence.
  • Coding was performed in Verilog and implemented the circuit on Programmable Logic Device.

Tools Used: Xilinx Vivado, Nexys2 Digilent FPGA, Schematic editor.

Implementing Artificial



  • The aim was to create and implement a technique of image compression using Artificial Neural Network
  • Implementation was done on FPGA for which the coding was done in Verilog.

Tools Used: MATLAB, Chipscope, Xilinx ISE.

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