EXECUTIVE SUMMARY:

• High Performance Embedded Computing and Communications expert with experience in designing and developing systems for extreme low latency communications, and super - computing on FPGA multi-core.
• These systems can perform high-frequency equities/derivatives trading and robotic controls in real-time.
• Expert at creating technical breakthroughs, bringing together management and technical teams and introducing innovative products to solve business problems.
• Domain expertise includes Financial Modelling, Quantitative Analysis, Trading Strategies, Derivatives Pricing and Risk Management with Statistical Computing.
• Professional experience includes High Performance Embedded Computing, Parallelization of Code on Multi-Core, Super Computing on FPGA’s, High Frequency data analysis for Fintech, Relativity Computing, High Speed Network Communications & Protocols on Chip-Microcontrollers.

CORE COMPETENCIES:

• Deeply pipelined systolic-array based hardware architectures to maximize computational/communications throughput.
• Ultra-High Speed back-bone solutions for trading firms and connectivity of stock exchanges using Low Latency technologies and HPC - Hyper Scale clustering with InfiniBand technologies using FPGA’s and GPU’s for performance optimization.

TECHNICAL SKILLS:

Networks: Trading Infrastructure Technology Products with HPC based Network solutions for Co-Location, inter data-center connectivity using FSA protocol over WAN/Internet and MSMI Protocol.

Communication Protocols: TCP/IP, FSA (Flow State Aware), Proprietary Metal Shared Memory Interconnects (MSMI).

Op. Systems: FPGA/BSD, Solaris, Micro Controllers, RTOS - VxWorks.

Technologies: FPGA/Verilog, C/C++ - Multi-core Programming, HPEC, FPGAs/GPUs, SoC, PYTHON, OOAD, PERL, MATLAB, InfiniBand, ClearCase.

Financial Technologies: Derivatives - Equities/FX/Commodities, MRM, CRM, ERM, Investment, corporate, and commercial bank offerings across asset classes in HFT-High Frequency Trading, SORs, FIX, order execution, order management, Basel II, MiFID.

Quantitative: Financial Modeling/Mathematics/Statistical techniques, Numerical Methods, Complex Monte Carlo simulation, PDE’s and Fourier analysis.

PROFESSIONAL EXPERIENCE:

Confidential, Santa Clara, CA

Senior Software Engineer

Responsibilities:

• As a senior software engineer my responsibilities include to arrive at a solution for the age-old communications problem i.e. TCP/IP which is slow and did not keep pace with the advancements of hardware technologies.
• My responsibilities are to architect and develop new High-Speed Communications protocol by taking the advice from the inventor of the internet Dr. Larry Roberts. The new protocol being developed is FSA protocol i.e. (Flow State Aware) which replaces TCP/IP in due course of time.
• The technology and the concept to overcome the legacy TCP/IP protocol are from my Ph.D. thesis “MSMI” protocol which was developed on HPEC, but the FSA protocol technology is based on HPC (High Performance Computing) on existing computers on x86 architectures.
• The “Alpha” version of the product is developed and released, and we are going to develop the “Beta” version.
• The Alpha version being tested in Citi group (BCM Markets) and VxChnge (Large Data Centers in US) R&D labs.
• Beta version is to be released by 2019 Aug. to the world and will be used in all communications companies .
• TCP/IP can never provide flow rates greater than 120Mbps though the cable that it is being deployed is capable of transferring 10000Mbps rates. If the distances are trans-Atlantic or trans-Pacific, its rate will be far below than 120Mbps. The same is true either on fiber or micro-wave as the fundamental protocol that drives the communications is TCP/IP. Successfully achieved speeds above 5Gbps rates with 2000mile cable.
• Provided multi-core parallel programming in processing millions flows at a time by making use of latest hardware technologies of fast memory technologies and superior algorithms to speed up the communications.
• Unlike some co. ’s in the market who achieved some success in solving TCP/IP problems by edge-based solutions i.e. doing patchy work before the switch, FSA provides intelligence to the network and it is a new protocol.
• Protocol can speedup and saturate TCP/IP traffic up to 20M flows of communications traffic in trans-Atlantic trunks in real-time.
• The rates that FSA protocol can achieve so far are 5.0Gbps on 10G trunk of 2000miles, this was tested on live wire between Santa Clara and Austin.

Technologies: X86 - architecture/FPGA, Embedded C/C++/Verilog, BSD, Networks/Telecommunications.

Confidential, Sunnyvale, CA

Senior Developer

Responsibilities:

• Designed & developed a system for “Automation of Parallelizing Sequentially written code on Multi-Core to achieve Super Computing”.
• Designed and provided architecture for “Compute-Communicate Continuum Technology - CCCT”, to build new breed of computers to achieve distributed computing to perform beyond Turing’s machine.
• Designed and developed a new high-speed communications protocol, “Metal Shared Memory Interconnects”, based on “High Performance Embedded Computing” HPEC technology.
• Designed and provided architecture for “Distributed Automata & Fabric as System Technology”.
• Turing scheme works well in one location/market but to work in multiple locations/markets requires other kinds of computation models with a different attitude towards the space-time patterns. To make Turing Scheme truly universal this technology can design and develop a new computer model i.e. a Distributed Automata wherein multiple CCCT-nodes work in unison at geographically distributed locations providing distributed computing.
• Proposed and provided architecture for “Relativity Computing Technology” to provide supercomputing with Distributed Automata built based on CCCT.
• The proposed computing model based on relativity computing is complementary to Quantum computing. The proposed relativity computing makes use of Einstein’s space-time equations in the computer model and achieves supercomputing.
• Provided consultancy to Confidential in Architecture, Design and Development of Robot - MPC - High Performance Computing - Robot Motion Control Software.

Confidential, New York, NY

Responsibilities:

• The present problem is interpreted on single processor environment sequentially and the response from the existing system will slow and when any parameter is changed it takes the same amount of time in responding.
• The above command statements made to run on multi-core environment working parallel on many cores. Executing the above command on multiple cores on FPGA or on conventional servers makes the response to be at wire speeds.
• The solution provided interconnects two exchanges TMX & HKEX by a fabric of FPGA based devices and these devices act on multiple roles as a matching engine at the CO-Lo of exchanges, clearing engines at the clearing houses, and also as a Gateways at the brokers/service providers facility. Though all these devices act as one system their functional behavior should determine the superimposed characteristic functions.
• Proposed systems design and architecture supports converged strategy for data procurement from different sources f content streams form both TMX and HKEX and distributing the same to hundreds and potentially to thousands of end users ranging from Financial Service Providers (FSPs) /DMAs and Brokerage houses the final consumers of the market data. The architecture of proposed fabric of systems deployment should be in consistent with the over-all design of the TMX-HKEX connectivity solution.
• Authored & Produced a detailed white paper for the management with complete architectural design.

Technologies: FPGA, Embedded C/C++/Verilog, BSD, Networks/Telecommunications.

Confidential

Senior Developer

Responsibilities:

• Developed a high frequency equities research infrastructure using MATLAB and Perl and then on C/C++ the prototype includes data filtering and processing to build various statistical modules (both graphical and computational) that allows to identify intraday arbitrage opportunities.
• Proposed architecture to analyse and test semi-automated trading system.
• Designed and provided architecture to set up no. of servers/market data feeds in different work environments (Dev./ QV/ Production), TAM authentication, Centralized LDAP authentication and authorisation, remote access, different servers/ applications access control as per the federal norms for Key Bank’s risk management system.
• Centralized access control system design management and coordination and proposed design for network set-up and variances for them as per federal norms.
• Provided low latency architectural solution for next generation Fix engine which connects no. of clients/exchanges and receives from clients/normalizes to DB format and demoralizes from DB format to Exchange /transmits the Fix messages. in real-time. Solution also involves real-time configuring client Fix rules, session’s management/data persistence controlling on multi-threaded/multi-core process environment.
• Provides real-time configuration of all Fix engines deployed with disaster management techniques.
• The complete solution is based on IB technologies which utilises RDMA techniques and variant TCP/IP protocols.

Technologies: X86 - architecture, C/C++/BSD, DB/Networks, FIX protocol.