Memory Design Engineer (Contractor) Resume Santa Clara, CA - Hire IT People

OBJECTIVE:

PROFESSIONAL EXPERIENCE

Memory Design Engineer (Contractor)

Confidential, Santa Clara, CA

Responsibilities:

Design low - power DMEM (2kx72) and IMEM (2kx54) Single-Port Cache-Memory with Redundancy using High-speed Dynamic Circuit technique for high-speed Bandwidth Engine chip.)
Design/implement custom high performance, low power and area efficient memory macros; SRAMs, Dual-Ports and Multi-Ports Register Files according to logic/architecture teams specs using custom flow with SRAM bit-cell from TSMC45nm. (Circuit design, schematic entry, layout extraction, margin analysis, timing/power char, timing model generation.). Perform back-end noise, EM/IR analysis and macro functional verification.

Staff Memory Design Engineer

Confidential, San Jose, CA

Responsibilities:

Design of Low-Power 28nm & FINFET for Samsung 14nm Single-Port SRAM Compiler (margin analysis, characterization timing and power, functional verification with ESPCV, leakage, EM/IR analysis, and back-end-flow, etc.)
Write and Read Assist scheme to improve margin at 14nm CP technology
Design of Single and Dual-port SRAM for memory compiler up to 1Mbit for cache application with multi banks architecture with redundancy for test & repair. Support optional features such as BIST, PIPELINE, and Power-Gating for leakage reduction.
EM/IR/SIGEM analysis and layout improvement with FINFET Technology.
Memory development flow, starting at design spec.
Optimize the timing path of L1 and L2 Cache level blocks for internal ARM processors.
Develop new circuitry and perform speed, margin analysis & characterization for all the compilers. Build up the physical instance of RAM through tiling and run formal FE and back-end verification for the whole compiler, QA and release the products.

Sr. Member of Technical Staff

Confidential, Santa Clara, CA

Responsibilities:

Design Multi-Ports Floating Point Architecture Register File for FGU unit using 3-D RF cell with two levels of sensing scheme and Transfer port.
Create the common library for Single and Multi-Ports Register File and involve in general methodology for designing both high-speed and low-power RF with the team.
Design and develop different types of CAM configurations, Dynamic circuits Methodology for ALU dynamic circuit design.
Participate in large designs taped out and silicon debug including running full-chip max and min timing, block regression with static timing tools.
Supervise IC Mask Designers to maximize the performance of the circuits from leaf-cell level to the production top-level layout.
Design Single/Dual port SRAM for memory compiler on 0.35um and 0.25um with IBM and TSMC process.
Perform timing simulation, schematic entry, debugging and characterization of SRAM sub-blocks (Sense-Amp, Control Logic, Decoders, Write Circuitry)

TECHNICAL SKILLS

SOFTWARE: Verilog,,C++, Perl, Sed and Awk, c-shell Programming.

CAD TOOLS: HSPICE, Finesim, Cadence Tools, Calibre, Simplex, Pathmill, Perl, RTL, verification with HSIM and ESPCV.

EQUIPMENTS: Oscilloscope, Spectrum Analyzer, Synopsys dc shell/Logic Analyzer.

TRANING: 16bits Computer Architecture Design (DSP processor design) with RTL coding, simulation, debug, and verification, Low Power SRAM.