SUMMARY:

• Looking for VLSI, ASIC design/management position in Semiconductor business
• 18+ year’s industrial experience Multi - Million gates product of Microprocessor chip Networking chip, Mixed signal DSP chip, Confidential .
• Experience of all phases of IC design from architecture spec to Layout.
• Leadership role with large team and multiple site projects.

TECHNICAL SKILLS:

Experience in: MATLAB, SIMULINK, C/C++, Perl, VHDL, Verilog, System Verilog, Synopsys DC, formality, Primetime, Fastscan, pathmill, SPICE, Opus, Cadence BuildGates, RTL Compiler, PKS, conformal, Silicon Ensemble, analog artist, spectra, hsim, testKompress, logicVision, VCS, modelsim, ncsim.

PROFESSIONAL EXPERIENCE:

Confidential, San Diego, CA

Senior staff Engineer

Responsibilities:

• Multi-core ARMv8 compatible Confidential for next generation flagship cellphone
• Work on Security processor subsystem on next generation multi-core mobile Confidential .
• Design security module to perform encryption and authentication on memory transaction.
• Use systemC and verilog to build the synthesizable core with AXI interface to CPU and memory.
• Utilizing algorithm to achieve maximum throughput for cache transaction to DDR
• Work include micro-architecture, systemC/Verilog design, verification, synthesis, and timing.
• Using integrated tool to perform DRC check on design quality.

Confidential, Irvine, CA

Principal Engineer

Responsibilities:

• Leading role on USB3.0 PHY (with 5G SERDES), mixed signal integration, analog calibration, digital design for analog test
• Leading role on digital DFT implementation.
• Experience on logicVision, testKompress, fastscan.
• Develop methodology for at-speed test running at 312.5Mhz.
• Leading role on full chip synthesis, STA, DFT, layout back annotation, gate simulation.
• Experience on 0.13um and 65nm process.
• Leading role on Full chip verification with system verilog testbench.
• Develop and document full chip testplan.
• Testing Confidential architecture with system verilog, c code and assembly code.
• Evaluate code coverage statistics.
• Support FPGA testing.

Confidential, CA

Principal Engineer

Responsibilities:

• Digital CMOS design with 0.13um BiCMOS technology SFI-5, SFI-S interface standard for channel deskew adjustment PRBS generator and checker Differential and DQPSK Encoder/Decoder Design spec development, RTL coding, Functional verification, synthesis, static timing, Place and Route Work on full chip verification.

Confidential, Hillsboro, OR

Senior Member of Technical Staff, design lead

Responsibilities:

• High speed mixed signal design Serializer/Deserializer full custom circuit design Timing recovery system simulation with MATLAB (simulink) Random data generator, FIFOs Digital Clock Data Recovery circuit: Phase detector, DSP filter, phase accumulator, phase interpolation, delta-sigma filter System integration of analog and digital parts System verification in hsim and spectra
• In charge of digital subsystem design team, project scheduling Architecture definition and RTL implementation of CCD timing generator Digital control and interface with ADC, DLL, CDS, PGA and other analog blocks Testbench development for full chip verification Synthesis, floorplanning and place route, DFT, power analysis, formal verification System integration of analog and digital parts System verification in hsim and spectra Supervising Layout design

Confidential, Portland, Oregon

Senior staff

Responsibilities:

• Microarchitecture definition and spec writing of Ethernet layer 1, layer 2 subsystem (PCS, MAC, buffering, queuing, traffic control), mapping channeled Ethernet data to SONET through Generic Framing Procedure (GFP) and HDLC protocol Implement Ethernet to SONET GFP/HDLC protocol RTL coding, testbench coding and logic verification Synthesis and scan insertion Static timing analysis, gate level verification Test vector generation and verification
• Work with Front-end design, back-end design and verification team in multiple sites Re-use various previously designed sub blocks with multiple clock domains Lead top level RTL coding and system integration.
• Combine and concatenate different SONET sub blocks to support ITU standard. Data rate from STS-3 to STS-192 Supervising system level verification and layout

Confidential, Hillsboro, Oregon

Senior Engineer

Responsibilities:

• Microarchitecture definition and spec writing of Pentium 4 Floating point subsystem, simulation with C/C++ or RTL on instruction scheduling, register file access, global and local writeback, speculative execution and floating point/MMX functional unit algorithm for performance/cost estimation Implementation of Floating Point/Integer/Multi-Media Multiplier, Multi-Media arithmetic unit.
• Implementation of Floating point reciprocal ROM Implement MMX2, MMX3 integer operation processor RTL coding, testbench coding and logic verification Schematic capture and custom design for datapath with static and dynamic circuit in transistor level, hand tuning transistor size for best performance.
• Circuit simulation with SPICE like tools.
• Synthesis with synopsys tool for control logic With both pre-layout and post-layout data, perform static timing analysis, backend verification including noise checking, electrical rule checking, gate level simulation, formal verification, etc. Scan insertion and scan vector generation and instruction based test writing
• Pentium 4 process shrink (Northwood. 3.0+ GHz)
• Work on compaction steps to fix logic bugs, timing path, and signal integrity issues