STAFF DESIGN ENGINEER Resume San Jose, CA - Hire IT People

OBJECTIVE:

Looking for a career in the area of Hardware Design where my experience, qualifications and analytical ability can be used in developing a new technology through innovative research.

PROFESSIONAL EXPERIENCE

STAFF DESIGN ENGINEER

Confidential, San Jose, CA

Responsibilities:

Responsible for leading the team in designing multiple low - density and high density EEPROM products with I2C and SPI Protocol Interface.
Responsible for architecture of the EEPROM IC.
Designed analog/mixed signal blocks like DAC converters, Charge pump, Sense-Amplifier, row and column high voltage drivers, oscillators, OpAmps, Voltage Regulator for the IC.
Extensive experience with running Eldo and Spectre simulators to simulate and validate block-level Analog and Mixed-signal designs.
Written RTL codes for the digital blocks and sub - blocks and verified in UVM environment.
Good experience using Design Compiler for synthesis of the RTL design and Primetime for pre-Route and post-Route timing analysis.
Integrated the digital and analog blocks for top-level chip.
Used Finesim simulator to run full-chip simulations for chip validation.
Optimized the architecture to have competitive die size and performance.
Worked extensively with layout engineers to tape-out product on schedule.
Designed and developed testmodes for post-silicon validation.
Worked with Product and Test Engineers for the characterization of the product.
Been able to deliver single revision products on-time to customers.
Responsible for leading the team in designing Single-wire parasitic power EEPROM product.
Responsible for defining the architecture of the design for low-power consumption.
Designed row and column decoders, oscillator and noise filters.
Responsible for Integration of Analog and Digital blocks at the top-level and validate the design at system-level.
Worked with Product and Test Engineers for the characterization of the product.
Delivered the product to the customers on-time.
Primary team member in temperature sensor team.
Responsible for the architecture of multiple remote and local channel temperature sensor products including DDR3/DDR4 products.
Designed Power-on reset circuits, Voltage regulators, Oscillators, Comparators, Voltage and Currents DACs, Voltage and Current References, Noise Filters, High-Voltage Drivers.
Primarily responsible for the algorithms and firmware development to measure out the Temperature for the remote and local channels.
Written whole firmware code for temperature calculations on the chip with custom micro-controller with custom instruction set.
Responsible for the validation of the design at full-chip level.
Written Built-in Self Test(BIST) codes for post-silicon validation and characterization of the IC.
Worked in NVM Flash memory product team.
Designed micro-controller and user interface for the serial flash and data flash products.
Responsible for the algorithm and firmware for the flash memory operations.
Responsible for BIST codes to test the product post-silicon.
Responsible for improving existing analog/mixed signal blocks like sense-amplifier to improve the performance of the device.
Strong Knowledge of physics behind EEPROM and Flash memory devices.
Solely responsible for the whole chip design and validation for some the derived flash memory devices.
Extensive experience in writing RTL verilog codes for the flash products.

Confidential, Fort Collins, CO

Responsibilities:

Worked as Research Assistant in VLSI LAB at Confidential . My research projects focused on the critical issues in deep submicron CMOS technology mainly in the Clock Distribution scheme, skew analysis. Enriched the mathematical model of Montecito clock tree with several other parameters to accurately estimate the skew. Other projects I involved include studying leakage power and its reduction techniques and Soft Error Rates
Worked as Research Assistant in Magnetic Resonance Imaging (MRI) Lab at Confidential . The work in this lab is to build a Radio Frequency Coil for MRI applications. These RF coils are used to scanning and imaging different samples.

TECHNICAL SKILLS

Synthesis/ Simulation Tools: SPICE,PSPICE,HSIM,Finesim,Modelsim, Esim (ELDO, Accusim),Xcalibre/caliber, Quicksim, Pathmill, Powermill, Nanosim.

Schematic/Layout Tools: Mentor Graphics’ Design Architect and IC Station,Cadence’s Virtuoso

Backend Tools: Design Compiler, PrimeTime, Encounter, Formality

Languages: C, VHDL, VeriLog, PERL

Operating Systems: Microsoft Windows, UNIX, Linux

Packages: Microsoft Office, Latex, MatLab, SIMULINK, Ocean Script

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Staff Design Engineer Resume

San Jose, CA

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