OBJECTIVE:

• To seek a challenging position as a CMOS/BiCMOS Senior Staff Mask Layout Designer in the areas of Digital, RF Analog and Mixed Signal designs.

SUMMARY:

• IC Layout Designer with over 18 years of experience in Full Custom IC Layout as well as in .
• Created layout for high speed Receiver and Driver Chip including IO pads and their ESD circuitry, RF, Analog, Codec, and Mixed Signal IPs, blocks, LNAs, TX, RX, DRX, PRX, Mixers, Bandgaps, Master Bias, ADCs, DACs, Comparator, Attenuator, C2C, R2R, PM, RCM, RCPSW, PLL, LDO, device matching, common centroid placement, layout of different pair circuit and different signal routing.
• Expert in layout floor and power planning, place and route of digital block that are not required timing, custom standard cell planning, and hierarchical layout assembly; Also expert in scheduling, and mentoring leads in my group in the US as well as in Bangalore of India.
• Experienced in CAD/EDA Engineering, Physical Design Verification Methodology and adaption of PDK in Cadence/Calibre environment.
• Good knowledge of SUN/UNIX/LINUX platform (Cadence Virtuoso VLE, VXL 5.1, 6.1, 12.1 and 12.2, L Edit, Avanti, Calibre, Hercules, Dracula, Diva, Assura, Cadence SoC Encounter RTL to GDSII…)
• Good knowledge of Mentor Calibre Verification tools such as: DRC, LVS, Soft Check, Antenna Check, MIM Caps Antenna Check, ERC, Custom Cell Checker, XOR or Compare, DFM, Via Hot Spot check, Single Diffusion Break Check, Density Check, LEFvsLEF, AbstractVsLEF, AbstractVsLayout, Schematic Versus Schematic, Float Gate Leakage Checker, DFM Pattern Checks, DFM Manufacturability Scoring, Litho Checker…
• Good knowledge of LEF/DEF generation tools.
• Previous experience in mask design for deep submicron silicon processing and familiar with different technologies and design kits such as TSMC (90nm, 65nm, 45/40nm, 28LP/RF/HPM/SOC, 20nm, 16FF, 7FF), 20GF, 28UMC, and Samsung (14lpp and 10lpe), IBM.
• I can easily integrate into multiple existing project teams, work, mentor, and supervise with other contractors or direct employees in the US as well as in Bangalore (India).

PROFESSIONAL EXPERIENCE:

Confidential, San Diego, California

Senior Staff Mask Layout Designer

Responsibilities:

• Recruited, built a Bangalore DAC Layout group of 20 members in 3.5 years; Have been constantly and maintaining this group ever since.
• Lead a group of mask layout designers in the US and Bangalore (India) laying out multiple designs of mask data for wafer micro - spring manufacturing.
• Reviewed and revised procedure documentation, and trained the mask and design group in proper design guidelines.
• Recruited and trained new members on both direct employees and contractors; have been giving monthly to mixed signal design groups of DAC, ADC, and PLL.
• Leaded, mentored new recruited leads; Headed a Quality Improvement Team that oversaw the root cause analysis of design errors and implemented corrective actions.
• Have been working closely with process, migration, pverf, dm, ESD, PD teams and making a greatly contributions for making tools more friendly for all users; also working closely with Cadence, TSMC, Samsung application and process engineers for testing new tools, features, then give s back to both design and layout community in mixed signal group.
• Decreased the number of design errors by 15% increment per quarter to a total of 35% improvement.
• Changed documentation, and implemented improvements identified by the QTI. Utilized root cause analysis and decreased the mask design cycle time by 40%.
• Currently working/leading/mentoring on multiple projects in TSMC28LP/28HPM/28RF/28SOC, TSMC20SOC, GF20LPM, TSMC16FinFet/7FF, SEC14LPP, and SEC10LPE projects such as TxDac, EtDac, WlanDac, ComboDac, RCPSW, Process Monitor (PM), RCM, Master Bias (MB), Rtuner, POR, DacVref, Bandgap, Attenuator, LDO, Comparator, C2C, R2R, MSB/LSB switch driver...
• Being co-lead of major chips such as: GZIP4, Marimba, Voltron, Torino, Elessar, Tesla, Sahi, Kichi Shere, Elessar, Hubble, Rex, Stingray, Chiron, CliffJumper, Hana, Snapdragon, Tachyon, Carrera 5G…
• Being lead on all layer changes on CODEC/BT chips; Completed CODEC, BT, DCO of RX & TX, ADC, synthesizer, DA, PA, VCO, PLL, LDO, SVIDEO, TX DAC, PC DAC, ET DAC, COMBO DAC, DSUB, TV DAC, WLAN DAC, RCP, POR, DAC VREF...
• Found several bugs with migration between IBM and TSMC 0.13UM processes and worked closely to the CAD members to resolve them all.
• Added diodes along the gates blocks-wide to avoid antenna issues in IBM process
• Completed it in timely manner. Created the LEF file and streamed them out in timely manner.
• Used bussing technique, matching devices to route wherever needed in blocks-wide.
• Did floor plan for the whole block and assigned works to members. Delegating and scheduling assignments for 6 layout designers, setting goals and priorities for each module, monitoring progress and milestones.
• To co-ordinate design and layout team on progression of block.
• Assisted members with his/her own floor plan, matching placements, routing, noise shielding, bussing, antenna issues, density, DRC, LVS, ERC, SCHECK issues throughout.
• I myself have completed GSM BB block; revised TIA block to meet engineers’ needed using bussing, common centroid matching. Also took care of resistance, capacitance as well.
• Completed DRX/GPS BB block 10 days earlier.
• Completed whole block 4 with all clean verifications and delivered 2 weeks before due date.
• Assisted engineers along with minor schematic changed.
• Found and reported several bugs of lvs and drc file to CAD group. Also worked close to CAD members to resolve those problems in timely manner.
• Completed all placements of WCDMA LNA HB & LB, GSM LNA HB & LB in timely manner due to the shortage of layout designers. Delegating and scheduling assignments for 5 layout designers, setting goals and priorities for each module, monitoring progress and milestones.
• Completed block GSM LNA HB to set an example for other members to copy the style on the rest of LNAs.
• Build rough inductors for model and design engineers to use as p.
• Completed block MIXER IQ GSM.
• Completed major revision of TXS TOP due to schematic changed.
• Found and reported several bugs with nmos4 rf, nmos6 rf models to CAD group; worked closely with CAD members to resolve those problems in timely manner. Also found and reported few bugs of drc, lvs file to CAD.
• Assisted members with synchronicity, drc, lvs, and erc, soft check issues.
• Completed RX top 1 week early and block BBRX TOP 2 weeks early.
• Completed revision block BBFTOP and its subs; and RXADC TOP and its subs due to schematic changed.
• Working with the layout and design lead for floor planning of RX, bumps locations, scheduling, layout resources.
• Delegating and scheduling assignments for 10 layout designers, setting goals and priorities for each module, monitoring progress and milestones. Assigned work to members and assisted them along with placement, routing, drc, lvs, erc, soft check, synchronicity issues.
• Assisted new members to create workspace, addling necessary libraries.
• Showed them how to use QVI verifications forms, RVE.
• Generated verification procedures for other members to follow.
• Hosted weekly meetings to share knowledge and educate team members on process technologies and verification related issues, particularly on common mistakes causing unnecessary reworks and extra verification time.

Confidential, Sunnyvale, California

IC Layout Designer

Responsibilities:

• Taped out several chips in timely manner.
• Worked with CAD engineers to correct bugs of models.
• Assisted engineers with schematic changed.

Confidential, Santa Clara, California

Computer Lab Instructor

Responsibilities:

• Tutored student(s) whom want to advance his/her self to higher level with detail lectures and practices on how to use the Cadence software to build up the chip.IC Mask Layout Designer: Completed dlatch, shift register, 512K DRAM, PLL, Bias, Clock Generator, Transceiver using Assura Drc, Softcheck, Lvs, Erc.

Confidential, San Jose, California

IC Mask Designer

Responsibilities:

• Responsible for Engineering Change Orders, edits an exiting layout to meet timing, robust, band gaps, metals revision and reliability specification.
• Run and analyzes sets of physical design verification tools including DRC, LVSH, LVSS, ERC, IR, XORs, BIAS, TAPE OUT.