SUMMARY:

• I am an SOC Verification Engineer with over 9 years of experience in implementing SOCs from Concept to Synthesis over Linux and Solaris operating systems. My career objective is to utilize my design/debug skills, creativity, and experience in the process of creating cutting - edge SOCs and position them to win.
• Performed pre-silicon verification of several peripherals on SOCs like PCIE, HDMI/HD-DVI, AXI, AHB, SPI, OCP, I2C, I2S, DDR3, GPMC etc.
• Developed unit-level and full-chip level tests and test benches in UVM.
• Developed unit-level and full-chip level tests and test benches in OVM.
• Fluency in Verilog, SystemVerilog, C, C++ and Perl.
• Experience in UVM RAL, VMM, SVA, Coverage, TCL and other software packages for EDA.
• Fluent in writing shell scripts and Make files in Linux & Windows operating systems.
• Developed/Executed tests for pre-silicon validation of bus interface units of Confidential 's x86 and Tensilica's Xtensa processors.
• Carried out post-silicon validation on chips with HDMI/HD-DVI PHYs.
• Experience with verifying graphics blocks, interrupt crossbars and clock generation units (CGU).
• Successfully designed, verified and synthesized configurable IP cores.
• Understand configurable ASIC/DSP/General computing chip architectures.
• Worked with standard design/synthesis and timing tools and methodologies.
• Hands on experience using oscilloscopes, signal generators and logic analyzers.
• Authored papers, reports and design specification/methodology manuals.

TECHNICAL SKILLS:

HDLs and Verification Packages: SystemVerilog, Verilog, UVM, OVM, VMM, Emacs Autos, System Verilog Assertions

Verification Tools: Cadence's IUS, Synopsys VCS, ModelSim's Questa, Verdi, Simvision

Vendor IPs: Synopsys PCIE, Snowbush Phys, Transwitch HDMI, ARM, MIPS, PLLs, DDFS, Tensilica xTensa processor

Vendor VIPs: Denali VMM VIP

Synthesis & Timing Analysis: Design Compiler, Physical Compiler, Buildgates (Ambit synthesis), PathMill, Leonardo-Spectrum

Other HDL Tools: Ralgen, ICCR, Spy Glass, HAL, Xilinx Foundation Series, Timing Designer

Languages: C, C++, ARM/MIPS Assembly, MATLAB, PERL, TCL/Tk, UNIX shell

Scripting, GNU: Make

IDEs: Visual Studio, Eclipse

OS: Linux, Unix-Solaris

Documentation: Adobe Frame Maker, MS-Word, MS-Project, Visio, Adobe PhotoShop

HTML Editors: FrontPage

Revision Control: SVN, CVS, TkCVS, Perforce, hg

Debug Tools: Fogbugz, JIRA, Bugzilla

PROFESSIONAL EXPERIENCE:

Confidential, San Jose, CA

Verification Consultant

Responsibilities:

• Debugged SPI UVC and wrote Reset release sequences for SoC verification.
• Developed UVM RAL Testbench and integrated it into full-chip verification environment.
• Developing Register Testcases and debug register related RTL.
• Verified the SPI to Internal bus transfer RTL at the SoC level. Wrote a Verilog SPI BFM at full-chip level for Test Development.
• Converting Ralf files into UVM register models using ralgen. Debug and update designers regarding Ralf files.
• As part of Full-chip verification team responsible for specifying and developing full-chip UVM test bench and test cases.

Confidential, Milpitas, CA

Verification Consultant

Responsibilities:

• Devised module level (ML) test bench in UVM for a distributed interrupt architecture called Interrupt Crossbar (INTX).
• Devised module level test bench in UVM for Clock Generation Unit (CGU) consisting of 26 clocks.
• Register programming for both INTX and CGU were done via OCP.
• Verified standardized performance counters (monitors) inside both INTX and CGU.

Confidential, Santa Clara, CA

Senior Design Verification Engineer

Responsibilities:

• Understanding the SoC architecture specification and PCI Express functionality requirements.
• PCI Express IP configuration recommendation based on functional, throughput and area analysis.
• Verification of integrated PCI Express IP & PCIE PHY into the SoC. The verification task involved not only port and memory connections but also control and status register and glue logic implementation.
• By client’s choice, ran test cases using Denali VMM VIP for pre-silicon verification.
• Setup MBIST test benches and run MBIST RTL/Gate simulations on customer ASICs. ( )
• Worked on integration of Confidential DDR3 into customer ASICs/FPGA and ran regressions. Performed FPGA feasibility and updated RTL for timing improvements ( )

Confidential, Topeka, KS

Design Verification Engineer (Contract)

Responsibilities:

• As part of the team developing imaging and video camera ICs, the work involved verification of I/O bridge IC (IOB) interfacing image sensor processors and other external devices.
• Member of full-chip verification team responsible for specifying and developing full-chip level OVM based Systemverilog test bench and test cases.
• Developed the test bench and the test cases for IOB’s GPMC slave interfacing with OMAP’s GPMC on one side and IOB’s AHB, DDR3 controller and proprietary monitor arbiter interfaces on other side. The test bench is written using OVM & SystemVerilog and was easily ported to run the full-chip regressions.
• Developed the test bench and test cases for GPMC & Xtensa processor stressing AHB interconnect inside IOB at the same time.
• Upgraded the existing test bench and Perl scripts for video/audio components of IOB. Developed & debugged audio-visual test cases for the same. Checked code coverage using ICCR.
• Developed a full-chip boot up test where in GPMC interface is used to activate Flash to perform calibration data transfer to DDR3 as soon as IC comes out of reset & program Xtensa processor to selectively transfer data from DDR3 to various interfaces that need the calibration data.
• Successfully upgraded the full-chip test bench to run the Gate-level simulations.
• Converted IOB’s RGMII interface Verilog test bench into OVM test bench for full-chip level integration.
• Supported FPGA team with FPGA based functional simulations of IOB.
• Supported OMAP device firmware development team with bring up of OMAP and IOB devices.

Confidential, Chandler, AZ

Digital Home Verification Consultant (Contract)

Responsibilities:

• As part of the multimedia group, the work involved verifying HDMI/HD-DVI components of a multimedia processor being designed for digital set top boxes, digital video recorders and other networked CE devices.
• Modified and debugged HDMI behavioral test bench model components by running tests in full-chip environment. The test bench is based entirely in Systemverilog.
• Developed, modified pre-silicon tests for verifying the video datapath through the input of HDMI MAC to the output of HDMI PHY in both DVI and HDMI video formats.
• Developed pre-silicon tests for verifying the audio/auxiliary datapath through the input of HDMI MAC to the output of HDMI PHY for all supported audio formats.

Confidential, Irvine, CA

IC Design Engineer II

Responsibilities:

• Member of HDMI/HD-DVI team, developing, upgrading & integrating HDMI/HD-DVI IP into Confidential SOCs.
• Support integration of existing HDMI/HD-DVI IP into Confidential ICs.
• Run the HDMI/HD-DVI regression suites to support ICs with HDMI.
• Debug and resolve any issues that occur in simulation regressions. Also expand on current test benches for existing DVI/HDMI IP.
• Run SDF back annotated Gate-level simulations for vector generation and taking them through the complete process of delivery to the test engineer in the post tape-out stage and follow up with the test engineer to resolve any issues that arise when the vectors are run on the actual chip.

Confidential

Component Design Engineer

Responsibilities:

• Worked on an innovative microprocessor for enterprise server applications. Being a vertically integrated design unit, the work is done right from the functional specifications to tape-out.
• Work involved feasibility study, RTL coding, validation and synthesis of the components in the interface protocol (BIU) of the microprocessor.
• Part of a team responsible for specifying, modifying and evaluating floorplan, placement and static timing results using physical synthesis tools.
• Responsible for synthesis, placement and timing analysis of two fubs in path to L2 memory.
• Devised synthesis procedures for conversion of custom design fubs into tool synthesizable fubs.
• Worked with design automation team on RLS (RTL to Layout Synthesis) tool flow issues and other technical requirements like automation of scripts for the same.

Confidential

Member Technical Staff (VLSI)

Responsibilities:

• Worked on configurable and reconfigurable computing architectures. Researched on functional specifications and converting algorithms into configurable architectures.
• Conducted feasibility studies of various viterbi decoder architectures for given specifications and carried out behavioral simulations using C++.
• Wrote RTL Code using Verilog and VPP.
• Created a self-checking configurable testbench with BFMs using Verilog tasks.
• Devised test cases and carried out functional simulations using Verilog XL and SignalScan.
• Gate-Level Synthesis and STA were carried out using Ambit.
• Checked Code coverage using CoverScan.