Applications Engineer Intern Resume Sunnyvale, CA - Hire IT People

SUMMARY:

Highly motivated, recent college graduate seeking a challenging career where I can utilize my chipset design and verification knowledge and the hands on experience with related EDA tools attained from various academic projects.
Looking for a Hardware full - time position in the field of ASIC/SoC Design and Verification.
1-2 years of experience in various engineering design process: product development, hardware validation.

TECHNICAL SKILLS:

Hardware Languages: Verilog, System Verilog

Programming Languages: C, C++

Scripting Languages: Tcl, Shell, Perl

EDA Tools used: Design Compiler, IC Design Studio, Pyxis by Mentor Graphics, Confidential VCS, Xilinx Vivado, DFT Compiler, TetraMAX, Matlab.

Environment: Linux, Microsoft Windows, Macintosh

PROFESSIONAL EXPERIENCE:

Confidential, Sunnyvale, CA

Applications Engineer Intern

Responsibilities:

Reviewed workbook and performed lab exercises to get working level understanding of the product.
Familiarized with CRM (SAP Customer Request Management) to understand the support tracking mechanism of Design Compiler.
Performed DC support Internal debugging, profiling and analysis techniques.
Analyzed DC defect status to understand the various nature of DC customer usage and reported issues in the areas of HDL, Optimization, and usability.
Simulated 54 test cases from various clients such as Apple, Samsung, Intel, Motorola, Altera, etc. using latest Design Compiler (2015.06) and established if it's a tool issue/incorrect usage and still reproducible.
Experienced with advance Design Compiler features, usage capabilities, TCL scripting, and UNIX.

Confidential, CA

Responsibilities:

Mentored, Conducted Lab sessions and assigned assignments/academic projects for a class of around 35 students.
Prepared tutorials for the DFT EDA tools DFT Compiler and TetraMAX ATPG which was used by the class students.
Evaluated the knowledge and skills of students on SCAN insertion, fault reporting, DRC check, and ATPG Test pattern generation using DFT tools.
Experienced with mentoring, DFT Compiler, and TetraMAX ATPG.

Confidential

CAD-Design Engineer

Responsibilities:

RTL coding using Verilog HDL for a chip that encodes and decodes data with parity bits based on Hamming function.
Synthesized with LSI 10k library, area, timing, and resources were reported using Design compiler.
Implemented RTL design of a MIPS single cycle processor in Verilog HDL.
Functional and timing verification of the design was done using VCS, Xilinx Vivado and synthesis using Design compiler.
Coded and verified an ALU design in System Verilog that can perform various logic operations.
The test bench can generate constrained random stimulus, run constrained tests, and can generate the coverage report.