Languages: Java, C, C++.
HDL: Verilog, System Verilog.
Scripting Languages: Python, Matlab.
Tools: Cadence Virtuoso, ModelSim, QuestaSim.
Version Control Tools: IBM Clearcase, IBM Clear Quest, Github, SVN.
- Responsible for integrating different Middleware components and validating the feature through the use of systematic test cases to develop, apply and maintain quality standards of Cisco products.
- Gathering feature requirement and preparing impact assessment which include functional requirements, requirement matrix and test plans.
- Implementing the test plan and designing the test cases and closely coordinating, identifying and analyzing the bugs and reporting major development/design issues to the corresponding teams and proposing bug fixing.
- Responsible for complete delivery of feature with regression testing of existing test scenarios.
- Analyzing the regressions and characterizing them and helping the component owners in fixing the bugs to contribute towards maintaining stability of middleware code as well as customer projects.
- Developed an android app which sends the real time location details to a remote web server and gets a response.
- Developed login and signup features. Used SQL database to store the user details.
- Implemented Google maps place picker to get the location.
- Simulated a DDR3 memory controller using In - order, no access scheduling, open page policy.
- Implemented a queue using linked list data structure to handle to requests.
- Designed Confidential for a fixed feed-forwarding neural networks.
- Implemented five stage pipeline processor and achieved a throughput of 120Mbps and latency of 200ns.
- All the Data, structural and control hazards are handled.
- Wrote verification plan, and implemented it. Unit level and chip level verification done. System Verilog assertion are used.
- Implemented checkers, scoreboard, Coverage.