TECHNICAL SKILLS

• Java
• JEE
• JSTL
• JDBC
• Spring
• Struts 1
• Tomcat
• Eclipse IDE
• SQL
• MySQL
• SQL Developer
• Perl
• HTML
• JavaScript
• Verilog digital design modeling
• Linux/Unix
• CVS version control configuration management with DesignSync and ClearCase.

PROFESSIONAL EXPERIENCE

Java Development Program

Confidential

Responsibilities:

• Designed a web - based calendar tool using Java, Java EE, JSTL, JDBC, and MySQL. The calendar tool allows users to schedule free-form tasks, and also incorporates a wizard to guide the user through selecting from among common tasks. Scheduled tasks can repeat either on a numbered day-of-the-month basis or a on a relative weekday basis (ie. 2 nd Tuesday of each month). Scheduled tasks can also repeat at a user-specified frequency on a month-wise boundary.
• Developing a web-based tool for recording when health care workers in institutional settings attempt to administer medications to a patient, and whether the patient ingests or refuses to take the medications. This tool addressed the problem of the inaccurate documentation of whether medications are taken by some patients. In many settings health care workers document that they've dispensed medications, but they do not accurately record instances of patient refusal to ingest medications. This tool proposes to correct this documentation failure by requiring the health care worker to separately document the dispensing and ingesting of medications. Technologies used include Java, Java EE, JSTL, JDBC, and MySQL.

Confidential

Junior Java Development Contractor

Responsibilities:

• Fixed Java and JavaScript coding errors by investigating incorrect behavior in Eclipse IDE and implementing fixes. Most business code was developed applying the Struts 1 framework, which required self-study to learn the basics of Struts. Additional skills and technologies applied in this role include Eclipse IDE, SQL, SQL Developer, and HTML.
• Corrected SQL Injection risks by converting code to use prepared statements.
• Mapped JSP pages to determine how to reach every view page in the code base.
• Wrote basic Junit tests.

Confidential

Responsibilities:

• Voluntarily left full-time employment as a chip design engineer with Freescale to attend to an illness of a family member.
• Worked as a full-time caregiver, until enrolling in the Java web development program at Confidential (ACC)

Confidential,

Digital Logic Designer

Responsibilities:

• Successfully lead a cross-site team of two engineers, located in Confidential, in the development of a Verilog model for a configurable, general purpose IP module which manages data stored in polysilicon fuses. The module integrates with a fusebox through a proprietary interface for programming and reading fuses, sorting data, and loading/acquiring data to/from a set of architected registers. Delivery of this component was a quarterly milestone for the division V.P., and was seen as a success due to on-time delivery and correct function.
• Developed the specification and micro-architecture based on discussions with internal product development team customers in different business groups. Presented specification proposal to customers, highlighting the specific needs of each one. Satisfying the requirements of different business groups was a critical requirements of this project.
• Partitioned the work into blocks which enabled a clear understanding of the function of each component and a clear understanding of the operation of the entire system, to minimize risk and design complexity.
• Held weekly status meetings with the engineering team to monitor progress.
• Compiled weekly engineering progress reports into a single weekly project report for senior management.
• Developed Verilog software models for several modules, including a digital logic circuit called a state-machine, which implement algorithms that make decisions based on history and current inputs.
• Developed a tool flow and wrote Perl scripts to pre-process data from Pathmill for a proprietary signal integrity CAD tool, and used the tool chain to analyze signal integrity compromised by coupling capacitance.
• Contributed in various roles during the development of a network infrastructure microprocessor.
• Designed error correcting code (ECC) logic based on the Hamming code, for detection of data corruption of a pass-code key used to secure access to the SoC.
• Owned the integration of a major block. This was a position of responsibility for enforcing product quality. Delivered releases of the block according to a schedule. Re-enforced expectations to team members of the delivery schedule for components, and monitored actual delivery performance. Evaluated the quality of the component models as they were released.
• Performed clock domain crossing and data convergence analysis for a major block to identify paths without proper synchronization. Worked with sub-block logic designers to evaluate all paths, implemented waivers for paths with use-cases which eliminated the need for synchronization.

Confidential

Digital Logic Designer

Responsibilities:

• Developed Verilog software models of various digital semiconductor components. Key tasks included:
• Implemented new functionality to expand the features of the previous generation design. Analyzed failing tests and implementing logic fixes.
• Performed logic synthesis using Synopsys. Created timing constraints.
• Developed directed assembly tests to investigate functionality of the register file logic.
• Debugged intermittent simulation errors seen in the results of Verilog VCS simulation. This was a role of considerable consequence since the errors encountered rendered all computer simulation results to be questionable. Determined the problem to be inconsistent coding of models, and proposed the solution that was implemented. Re-coding models following my recommendation fixed the problem.
• Developed a Verilog model of an IIC-compatible bus interface, for a video compression encoder/decoder. Key tasks included:
• Specified the block functionality. A subset of the IIC protocol specification was implemented.
• Developed a Verilog model, including an 8-state state machine.
• Developed a testbench for evaluating the model.