Sr. Layout Engineer Resume

SUMMARY

Seeking a position as a Mask Designer.
SUMMARYHands - on experience in IC MASK Design, verification using Cadence Virtuoso-XL/Opus, Assura & Dracula DRC/ LVS, Encounter, Calibre DRC/LVS and Magic.
Hands-on experience in Cadence SKILL programming, C, Perl and UNIX shell scripts.
Knowledge of CMOS process concepts and layout techniques, Latch-up theory and prevention techniques, ESD and protecting techniques, Floor planning concept, matching, noise, high frequency issues, Bipolar and analog circuits.
Knowledge of Verilog HDL and UNIX Operating system.
Extensive training in IC Mask Design using Cadence OPUS, Cadence SKILL programming.
Strong desires to learn and explore new technologies.

PROFESSIONAL EXPERIENCE

Sr. Layout Engineer

Confidential

Responsibilities:

Implemented analog custom layout including 4G PLL, Continues Time Linear Equalizer, Slicer, Phase Interpolator and Serial to Parallel converter.
Implemented Bandgap reference.
Implemented analog custom layout including 12 bit SAR ADC, Charge integrator, Analog Filter, LDO and TX/RX buffer.

Sr. Mask Design Contractor

Confidential

Responsibilities:

Implemented analog custom layout including PLL, output driver and digital interface.
Implemented layout porting from different projects.
Implemented analog custom layout including LDO, DAC, low noise FGA, input/output buffers, etc

Sr. Mask Design Consultant

Confidential

Responsibilities:

Sr. Mask Design Consultant

Confidential, San Jose, CA

Responsibilities:

Sr. Mask Design Engineer

Confidential, San Jose, CA

Responsibilities:

In depth understanding of RFIC design requirement.
Built custom layout to match devices, shield critical signals to ground line for noise reduction.
Implemented PLL layout including voltage reference, phase detector, charge pump, VCO, ESD device, bonding pads and bus planning.
Built custom layout of various analog devices including Mixer, LNA, IF filter, power amplifier, DAC, bandgap, etc.
Implemented top level chip integration and tape out activities.
Building Pcells such as Guard-ring and stacked via, etc.
Implemented SKILL routines for layout and schematic library checking, schematic tree search, and floating gate checking, etc.
Implemented DRC rule files.

IC Layout Designer

Confidential, Sunnyvale, CA

Responsibilities:

Performed CMOS IC layout design in 0.18um & 0.35um technology using Cadence OPUS, Dracula, Mentor Calibre and Hercules.
Built custom layout of the various SRAM leaf cells including row decoder, column decoder, Read/Write circuits, and peripheral interface cells etc.
Proficient in Standard Cell Layout: complex logic gates, D flip-flops, latches, storage registers and tri-state buffers, etc.