SUMMARY:

• SOC ASIC designer & CAD engineer with nine years of mixed - signal experience in custom and full APR IC design, CAD, and development engineering roles. Involved in high speed digital and mixed signal designs for memory, communications, and RF applications.
• Experienced SPICE and Verilog user, with expertise for solving IR, EM, SI and timing closure issues in pre-silicon and post-layout issues using industry standard tool flows.
• Custom IC design & RTL-to-GDSII implementation including floor planning, power planning, routing, I/O placement, cell placement, clock tree synthesis, parasitic extraction and back-annotation, static timing analysis, and formal verification.
• Most recently, supported over 200 FLASH memory design and layout engineers at multiple sites on Cadence custom AMS & Synopsys APR flows for Confidential .

TECHNICAL SKILLS:

Design Tools: Verilog VCS, Verilog XL, NC-Verilog - Synopsys APR & Custom Design tools - Design Compiler - PrimeTime & PT-SI - HSPICE - Astro, Astro-Rail and Star-RCXT - Hercules - Cadence APR & AMS design tools - First Encounter - Spectre, UltraSim, AMS Designer - CeltIC - Mentor custom design flow - Eldo - xCalibre - VERA - Modelsim - Virage Logic s memory compiler tools - Zeland s IE3D Ansoft s HFSS Xilinx FPGA/CPLD Modelsim JMP

Software Skills: unix shell scripting MatLab Javascript - Perl - Tcl/Tk - C/C++ - Microsoft Excel, Word, PowerPoint - behavioral and synthesizable Verilog coding - JMP statistical analysis

PROFESSIONAL EXPERIENCE:

Confidential, San Jose, CA

CAD Applications Engineer

Responsibilities:

• Resolved user & tool issues with the environment, made improvements by modifying or creating shell & Perl scripts, trained new users on the environment.Flow Improvements: Evaluated Novas’ Siloti tool for suitability in Micron’s digital design flow, working extensively with designers and Novas support personnel to optimize tool for Micron’s requirements.
• Cross-Probe: Performed a capability ‘roll-out’ for Cadence Virtuoso & Hercules schematic-to-layout cross-probe net highlighting capability that explained and documented ways of tracing nets within and between schematic and layout.
• Trained over 60 designers and layout personnel to use the functionality for cross-probe and LVS/DRC checks. Improved tool flow from feedback gathered in 1:1 & group s.
• Documentation Overhaul: Took all 18 individual Micron FLASH design guideline documents that had over time diverged extensively, and improved them for clarity, style, and readability. Received management praise for quality of work and document re-convergence.

Confidential, Santa Clara, CA

Senior Component Design Engineer

Responsibilities:

• ‘Look-ahead’ CAD role that researched and solved anticipated design problems, process selection and process requirements for hand-held, wired and wireless communication chips for 0.13um, 90nm and 65nm designs.
• APR Signal Integrity: analyzed needs of Confidential communication chips on TSMC 0.18um and 0.13um processes, brought in signal integrity automated analysis for APR designs at 90nm node for the Confidential ICG (now Mobility Group).
• Optimized APR flow to include signal integrity, worked across functional teams to gain acceptance for tool and implement flow.
• Power grid planning: Designed & implemented a tool for RV/EM requirements using Perl, SPICE, and MatLab, for rapid testing of proposed power-grid solutions
• Transistor-level Design: Provided memory cell and architectural changes for a single poly FLASH NVM 90nm process. Provided implementation, manufacturing and test plan to design team and management for adoption.
• User Enhancements: Built an ‘advisor’ website for circuit designers to provide BKM ESD techniques for several IO designs, providing layout and SPICE simulation.
• Thermal Package Modeling: Investigated thermal impact on cost competitiveness of Confidential flip-chip VS TSMC wire bond for low-volume, high-mix communication (ICG) parts.
• As a member of a cross-organizational team, drafted main report and participated in presentation to senior management.
• Competitive Analysis: Showed potential savings for Confidential communication group by improving design of Confidential register file & compiled SRAM memories through compiler design style comparison, HSPICE and Verilog circuit simulation, and die size area impacts. Proved over-design for large memories was killing commodity part competitiveness.
• Architecture: researched low-power design and architectural changes for high-speed analog communication products for enterprise switch chips moving from 90nm to 65nm, modeling noise, leakage, area and power requirements using Cadence tools.
• Substrate Noise Coupling: lab-measured digital noise impact on analog high-speed IO (XAUI 10GBPS) performance of 90nm Ethernet switch chips to predict 65nm behavior on low and high-resistance substrates, presenting results to management. Modeled VCO behavior in SPICE for Ring Oscillator and LC-Tank circuits to compare jitter trade-offs.

Confidential, Austin, TX

Custom IC Memory Designer

Responsibilities:

• Design responsibilities from transistor-level SPICE simulation through Verilog models and testbenches of SRAM & ROM stand-alone & SOC memory chips. DDR, LVTTL, HSTL & PCI interface modeling. Supervised layout designers to ensure compact and correct match of design to schematic function. Designed JTAG & BIST circuitry.
• Design: created repair scheme and address decoding for redundancy circuitry of replacement column & rows for correction of bit cell array defects in an embedded SOC ROM, implementation of a hardware error-correcting code (ECC), dual-detection/single-replacement.
• Verilog: wrote testbenches for stand-alone SRAM and embedded SRAM & ROM memories for full chip and smaller blocks--JTAG, control & data path operation.
• Signal Integrity: package IO noise modeling for Vdd/Vss noise reduction. Results were used to improve C4 power grid layout & signal trace-route optimization.