Developer Resume

SUMMARY:

Good understanding on ASIC Verification cycle, SoC, Directed test suite, Cache Concepts, System Verilog, UVM methodologies.
Worked on 3 IP verification projects and 4 SoC verification project.
Development of test bench component like Scenario Generator and Driver.
Verification of Intel specific PMI2AXI bridge in subsystem level and PMI BFM Development for standalone PMI2AXI bridge Verification
Verification of ARM DMA Controller (PL330) in Cortex A9 and Cortex R4 based SOC.
Development of Block Level Test Plan.
Run Regression and collect Code coverage and Functional Coverage.
Develop code to verify the memory map of SOC by writing/reading data to start.
Address and end address of different memories like SRAM, DDR from processor.

TECHNICAL SKILLS:

Programming Languages: Verilog, System Verilog, Assertions (SVA) and C

Methodology: OVM, UVM

Technologies: CACHE, DMA (PL330), SOC,AXI, Memory Controller, I2C, PMI, IOSF - SB, GLS

Tools: Cadence NcSim, Synopsis Verdi, Questasim, ModelSim, Xilinx ISE

PROFESSIONAL EXPERIENCE:

Confidential

Responsibilities:

subsystem level: Worked on the hook up of the AXI BFM for PMI2AXI bridge in sub-system, Developed test case for any RTL update, Running the testcase and debugging the failures. standalone level: Developed the scoreboard to compare the data at the PMI input interface with the axi output interface. Also worked on the PMI bfm for the the request/input side stimulus generation for pmi

Environment: Directed / Random environment (Synopsis, Verdi, assembly UVM and SV based)

Confidential

Responsibilities:

Development of Block Level Test Plan .Build API’s to support DMA test’s. Developed instruction set file for M2M, M2P and P2M DMA supported transfers. Coding directed test cases. Running the test cases and debugging the failure. Functional coverage development and analysis. Performance number calculation for DMA read/write Run Regression and collect Code coverage. Perform DMA Data transfers between diff memories and peripherals across SOC like SRAM, DDR, UART and IPC. Coded DMA real time usage tests to help post-silicon validation for DMA data transfers with only frontdoor access using instruction set encoding of DMA.Worked on GLS for developed tests.

Environment: Directed environment (Synopsis, Verdi,C, assembly and Verilog based)

Confidential

Responsibilities:

Intergration of the synopsis I2C VIP. Development of Block Level Test Plan. Coding of test cases for VIP to generate stimulas. Running the test cases and debugging the failure. Run Regression and collect Code coverage. Worked on GLS for developed tests.

Environment: Directed environment (Synopsis, Verdi, assembly UVM and SV based)

Confidential

Responsibilities:

Development of Block Level Test Plan for I-Cache 32-KB, O-Cache 32-KB and L2-Cache 256-KB.Coding of test cases for 2-Way I-Cache and O-Cache. Coding of test cases for 4-Way L2-Cache.Running the test cases and debugging the failure. Monitoring the Cache-hit and Cache-miss registers to check the correctness of test.

Environment: Directed environment (Cadence NcSim,C, assembly and Verilog based)

Confidential

Responsibilities:

The objective of the project is to stress SoC under different conditions like simultaneously triggering multiple IP’s and verify the memory mapping of different memories and ROM code and check all the processors in the SOC support all possible kinds of burst size transferand unaligned transfer.
Development of Block Level Test Plan .Coding of test cases and interact with multiple IP owners in the project and code test which has many IP’s working simultaneously like DMA, Ethernet and I2C.Develop code to verify the memory map of SOC by writing/reading data to start address and end address of different memories like SRAM, DDR from processor. Check all unaligned address access supported by all the processor across different
Memories in different sub-system in SoC. Develop test to check ROM code is placed at desired location and matches with expected. Running the test cases and debugging the failure .Run Regression and collect Code coverage.

Environment: Directed environment (Cadence NcSim, C, assembly and Verilog based)

Confidential

Responsibilities:

Development of test bench component like Scenario Generator and Driver. Test Case development. Running the test cases and debugging the failure. Run Regression and collect Code coverage and Functional Coverage

Environment: Questasim, System verilog

Confidential

Responsibilities:

Development of Packet Class, Interface, Sequence Generator. Coding of test cases. Running the test cases and debugging the failures. Run Regression and collect Code coverage and Functional Coverage.

Environment: Questasim, UVM