OBJECTIVE:

To provide innovation, technical expertise and leadership. To promote an agile team mentality. To improve the world about me with my passion and drive for excellence. I succeed and find solutions. Summary of Work Experience: I am an innovator in electronic, mechanical design and material science with significant expertise in High Speed Digital, Analog, Switch Mode Power Supply (SMP), DSP, CPU, MicroController, FPGA, and CPLD, Wireless Pwr, complex PCB/Flex layout applied to Medical Ultrasound,Military, and Consumer electronics applications.

SKILLS:

Practical thinking and a striving for excellence mark my path. Out of the box, flexible, innovative with various patents in every company Iv’e worked with.

CAE tools: Altium, Orcad, Viewlogic, Modelsim, Hyperlynx. Experience interfacing with Allegro, PADS, EPD,

Programmable logic: Altera, Xilinx FPGAs and various CPLDs, PALs

Processors: Broadcom, Nordic, Cypress, TI Davinci, Xeon Pentium IV & III, TMS320C6713,01, TMS320C80, MC68340, 8085

OS & Languages: Unix & PC environments; VHDL, C.

Busses: PCIe, cPCI - X, VME, SMBus, I2C, USB, SPI, RS232, IEEE1394, DVI,

Lab skills: Very Strong with Agilent & Tektronix logic Analyzers, Scopes, Network/Spectrum analyzer, Emulators, TDR

System design: Able to translate customer goals to realizable specs and from there to optimal design approaches and architectures

Design & Debug skills: Excellent in high speed multi-layer circuit board design (Rigid and Flex), ECL, LVDS, EMI/EMC, state machine design, PCB layout, moderate analog design (SPICE), wireless power (A4WP, PMA, QI, NFC), BluetoothLE, switch mode power supply, resistive and capacitive touch design, mechanical, thermal design/analisys and design for testability and manufacturability.Fault Analysis, Mechanical (molding, milling, lathe) and Materials expertise

EXPERIENCE:

Confidential. San Francisco CA

Principle Engineer, Systems Architect

Responsibilites:

Architected and implemented mechanical, electronic, process and material solutions achieving unprecedented packaging reduction and market capture for consumer Credit Card sized product. Touch Screen, Biometrics, Packaging, Materials, Extreme low power, Wireless charging (A4WP, PMA, Qi, NFC), Custom analog battery management, EMV, NFC, Magnetics, Extreme Flex Circuit design. IC handling for Flexible electronics suitable for IOT, Wire bonding, ACF based EINK custom display & Touch Screen attachment. Team leadership, Customized IC’s, Test gigs and and manufacturing processes shepherded.

Confidential

Member of Technical Staff

Responsibilites:

Architected solutions to achieved unprecedented super - quite high power multi-output switch mode power supplies saving a troubled program from failure and securing the bottom line. Created architecture and significant code sections for a major VHDL upgrade to Sonosite s largest FPGA. This contributed significantly to the successful and timely product launch strongly supporting the company s bottom line. Created architecture and design details, leading a small agile team, for a SW beam forming engine using analog filters, ADCs, GigiBit data links and multiple FPGAs. I contributed signal integrity analysis, bus architectures, power supply design of 5 PCBs up to 20 layers with blind/buried/microvia along with 4 mechanical assemblies. I architected 7 unique bus designs/protocols supporting bit rates up to 1Gbit/second, custom ultra high speed isolated interfaces, multiple switcher power supply designs, ultra low noise custom regulators, filters and A/D circuits added to the challenge. Contributed to break-away product. Patents US8527033B1, US8409095B1 issued.

Confidential

Staff Electronic Engineer

Responsibilites:

• zImplemented production line test equipment for Medtronic Corporation in a highly FDA regulated environment. Used Orcad to create new design library concepts to foster reuse.
• 1990/2 to 2006/7 Siemens Medical Solutions, Ultrasound 21010 SE 51st St., Issaquah WA 98027
• Senior Staff Electronic Engineer and Technical Lead
• Co - inventor of 3D & 4D stereoscopic viewing mechanisms for ultrasound imaging. Patent US7563228 issued
• Dual Xeon Pentium 3 & 4 based CPU system architecture and design team member.
• Technical lead and individual contributor for embedded processor group using TMS320C6713, 01 processors.
• Implemented C80 based ultra-high performance Image Processor enabling acclaimed Siescape functionality. Architected three additional image and Doppler processing designs. Co-authored paper with researchers from UW and published via Diagnostic Imaging. Innovative PLL based digital timing saved $2000 per board - US Patent US5767715 issued. Technique offered to Xilinx and Altera - now standard feature.
• Participated in system design elements of front end busses and timing. Member of Generalized Back-end advanced development team.
• Managed technical and personnel aspects of 15 member Beam-forming group. Led many other departmental actions including the introduction of VHDL, FPGAs, CAE tools, Clock Distribution schemes and introduction of JTAG & low voltage logic.
• Co-designed Image Memory board (VME D64 interface & 68340 CPU sections)
• Contributed heavily to new tools and technology process development. Created Multi-board hardware/software simulation technology - wrote 2 papers and presented at Synopsys Users Group.
• Designed adaptive Color Flow/Wall Filtering circuit boards then redesigned same as company s 1st ASIC. Patents US5653234 & US5494037 & US5664575 issued by US government for unique adaptive features.
• Designed and constructed custom data generator/recorder for back end debugging.
• Invented logic-analyzer to pin grid/ball grid array adapter - US patent US5949238 issued.