PROFESSIONAL EXPERIENCE:

Confidential, Camas, WA

Test Automation Engineer

Responsibilities:

• Developing automation test suite for Confidential commercial printer environment.
• Develop tools to generate artificial jamming in printers, copying, wireless printing on demand and other features without human interaction.
• Present, training and teach junior engineers on test automation and how to use test suite.
• Work with other firmware and software teams to integrate test suite in user flows.
• Integrated test environment to run automated test suites on Ubuntu (Linux) and windows platforms.
• Experience with Automated Test tools and frameworks using Python.
• Visual Basic, Python, C, C++, HTML, programming skills.
• Using Git and Github for version control

Confidential, Hillsboro, OR

Quality Engineer

Responsibilities:

• Test, design and automate test suite for firmware builds for android tablet devices using Python.
• Proficient in creating and executing test plans, test cases, and test reports using HPQC and other tools.
• Familiar with MKS, Confidential Quality Center automated testing environment.
• Visual Basic and SQL programming skills.
• Understanding the development and delivery of test plans, test cases, test reports, and program documentation
• Excel spreadsheets skills developing pivot tables using VBA and SQL queries from HPQC for defect reporting.
• Perl automation scripts used to generate XML file and other files for online manufacturing files.
• Work with the software development team to troubleshoot and remediate issues in production environments.

Confidential, Hillsboro, OR

Design Automation Engineer

Responsibilities:

• Debugging and developing Confidential internal tools and methodology using Perl, Python and other scripts.
• Responsible for environment and tool update and enhancements to release tree in simulation, build and runtime for validation team.
• Good knowledge debugging large scale applications using Linux and Windows and linux system administration
• Agile and Scrum team planning.
• Creating initial framework for testbench E code and functional level coverage in release builds for validation team.
• Clock domain crossing checks for large processor at full chip level.
• Specman DA responsible for reproducing, fixing and working with tool vendor to drive resolution on cadence tools.
• Verdi DA also responsible for reproducing, updating, patch and finding workarounds.
• Developing scripts and new tools to be used in project using Perl, SVN, bit keeper and GIT.
• Perl development, HDL debugging, E debugging, LEC.
• Coverage and Specman tool in house expert.
• Pioneered clock domain crossing tool (CDC) on top level blocks in KNL and associated bug reporting on CDC violations.
• Create automated coverage flow where specman coverage rolled up from DUTS and created reports.
• Converted GLS behavioral based library to UDP based with associated scripts and LEC for checking after conversion.
• Converted KNL env to do GLS/Behavioral cosimulation to compare results with E.
• Behavioral bus functional modeling using C and C++.
• Some C# and Java experience

Confidential, San Jose, CA

Sr Application Engineer and Verification Engineer

Responsibilities:

• Emulation model development and verification for Confidential emulation models and simulation.
• Cycle based simulation model development using internal cycle based simulator.
• Waveform generation using FSDB debug features and nCompare with Debussy/Verdi.
• RTL synthesis to gate level EDIF netlist targeted for Xilinx FPGA of 32 core design.
• Working knowledge of PCI Express 2.0 and DDR3.
• Detailed knowledge of System Verilog, verilog - 2001 and VHDL.
• Using and/or familiar with scripting including Perl, gawk and sed and gmake.
• Working knowledge of C++ and C.
• Code management experience in SVN and clear case like creating branches, release trees, tags, check in/out.
• Some experience with debugging and displaying assertion results.

Confidential, San Jose, CA

Sr. Applications Engineer and Verification Engineer

Responsibilities:

• Product expert in Verdi, nLint, nCompare, nWave, nState, nSchema, Siloti.
• Detailed expert working experience with ncsim, vcs and Modelsim and all their API’s to integrate to third party objects.
• Created specman tests and coverage for large communication ASIC.
• Software demos and presentations of Confidential feature set like Debussy, nLint, Verdi.
• Software training to new and existing customers.
• Wrote specman e tests and coverage analysis for customer designs.
• Detailed knowledge of System Verilog, verilog -2001, verilog and VHDL.
• Working knowledge of PSL, OVA, System C, Vera, specman E and transactions.
• Detailed knowledge of SOC ASIC flow from System level, RTL, gate to layout.
• Wrote several TCL applications for new software tools for production at Novas. This tool was integrated to Confidential PCB board schematic generator using C-Socket. C-Socket TCL experience.
• Territory included Pacific Northwest, Southwest region and Israel
• OVM and UVM training and working with large customer utilizing methodology.
• Working as tools and system verilog consultant.

Confidential, Beaverton, Oregon

Applications Engineer and RND Software Engineer

Responsibilities:

• Responsible for test, presentation, training and customer rollout of embedded 68HC11 and 8051 processor cores for ASIC design flows.
• Familiar with 68HC11 and 8051 assembly language code.
• Responsible for developing and demonstrating synthesizing DesignWare IP products at trade shows.
• Responsible for FAE/customer demos, presentations and training in Hardware Model, FlexModels, Mempro, VMC/CMC/VHMC simulation modeling technologies.
• Very familiar with Confidential ASIC synthesis Design Compiler tool.
• Demonstrate HW/SW coverification products at embedded system trade shows.
• Advanced C++ graduate class training, System C training, basic and advanced synthesis training.
• WindRiver embedded OS core training.
• Develop product demos for VMC/CMC/VHMC.
• Software development engineer using C in a UNIX and NT environment.
• Responsible for developing interface between FlexModel technology and supported digital VHDL/Verilog simulators.
• Extensive knowledge of Modelsim VHDL/Verilog, Cadence Verilog - NC/XL, Veribest Verilog/VHDL, Confidential Scirocco, Cyclone and VSS simulation products.
• In depth knowledge of VHDL/Verilog.
• Extensive knowledge of Make, PERL and UNIX scripts to run and verify software builds and release tests.
• Working experience with java and C++.
• Working experience with software debuggers such a gdb, dbx and ddd.
• Working experience with IP based tools such as VMC/VHMC and CMC.
• Working experience with Vera testbench language.
• Developed production software using Atria build and release environment.
• Performance testing using “Quantify” and memory checks using “Purify”.
• Responsible for Mentor Graphic’s “Swift Interface” and Hardware Model “Model Access” code.

Confidential, Wilsonville, Oregon

Technical Marketing Engineer

Responsibilities:

• Confidential netlist generation products.
• Developed customer presentations and demos on Modelsim, QuickSim II and Modelsim products.
• Wrote and debugged Verilog and Confidential designs using Modelsim.
• Field AE and customer training on Modelsim.
• Field marketing and customer support on technical aspects of all products supported.
• Performance testing and benchmarking.
• Customer requirements gathering for enhancements to Modelsim.
• Project engineering manager on VHDLwrite product.
• Customer trade shows at MUG 96 and 97, DAC 96 and IVC/VIUF 96 and 97.
• Have had TCL training and have some current working knowledge of TCL language.
• Have taken advanced VHDL, Verilog and PLI training courses.
• Customer support involving Modelsim, QuickSim II, System1076, Continuum and QuickHDL Pro simulation products.
• Wrote Verilog and Confidential to reproduce problems and verify functionality in Modelsim.
• Customer support project team member on FlexSim simulation project.
• Customer support involving Mentor Graphic’s technology file and BLM library models.
• Develop and/or debug customer test cases to reproduce software defects and develop timely work around
• Generated detailed defect and enhancement reports to engineering.
• System Administrator and ASIC librarian for digital simulation customer support team.
• Develop knowledge based solution records and customer support bulletins.
• Consistently had the top percentage of calls taken and best resolution time over one year period.

Confidential, Hillsboro, Oregon

Software Modeling and Q/A Engineer

Responsibilities:

• Wrote behavior modeling Verilog/C code to create Verilog based simulation models.
• Tested, debugged and verified functionality of Verilog/C models using Cadence Verilog XL.
• Quality Assurance (QA) Engineer for Confidential compiler and synthesis tool for cypress semi.
• Main duties included regression testing, analyzing, reporting to R&D and debugging Confidential compiler and synthesis software on a weekly basis for R&D engineering team.
• Wrote new Confidential tests (RTL and gate level) in order to test new features of Confidential compiler and synthesis tool.
• Modified existing Confidential tests in test suite to verify current functionality.
• Simulated and verified results of test suite using Cypress Semiconductor’s Simulation Toolkit.
• Wrote DOS scripts, automated and maintained Confidential test suite in a PC environment.

Confidential, Sunnyvale, CA

Hardware Design Engineer

Responsibilities:

• 6 years of digital signal processing design experience and analog design experience
• Front end design, simulation, layout and testing a PCB board consisting of CMOS logic families used in RADAR simulation.
• State machine and PROM firmware developed using C.
• Tested PCB board by generating C driven test vectors and UNIX shell utilities in card rack with other boards.
• Hands on experience using oscilloscope, logic and spectrum analyzers.
• Completed design project ahead of schedule and was Cfor 6 RADAR boards during HW/SW integration.
• Led design reviews on circuit card progress schedule.
• Designed, simulated, timing verified and packaged PCB boards for production.
• Design, simulation, layout and testing 5 digital and 1 analog PCB board used in SONAR simulation.
• Digital designs included a 4x128 - 64 point FIR filter PCB board, 8M x 8 bit DDRAM memory board, sum node and SONAR type algorithmic boards.
• ASIC development and testing.
• Analog design included a low frequency FM modulator with an AM modulated phase.
• Analog design contained 16x4, 16, 12 and 8 bit DAC's, op amp functions and drivers, oscillators, band and low pass filters, multipliers, rectifiers, triggers, regulators, caps and resistors.
• Designed, simulated, timing verified and packaged boards using simulation work stations.