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Product Definition & Application Resume

Chandler, AZ


  • Manage & Develop Power Management & wearable IC projects with 98% yield and cost optimization for consumer, industrial & automobile over 8 years.
  • Architect automotive semiconductor design according to ISO26262 standard.
  • Support automotive OEM and Tier 1 suppliers’ road test issues and system cost optimization.
  • Seasoned engineer in product development, new product introduction, yield enhancement & cost optimization, management & customer communication.
  • Design Project Manager experiences in IP development, project risk & feasibility analysis, planning, scheduling & resource management.
  • 10-year power management IC development experience.
  • 6-year design lead experience.
  • 5-year project management experience.
  • 4-year automotive development flow experience.
  • 4-year memory IC design experience.
  • 2-year automotive battery management experience.
  • 1-year image sensor design experience.


Operation System: Unix, Windows/NT

Design Applications: H/PSpice, Cadence Schematic/Layout Capture Tools, Cadence Analog Artist, Spectre, Ultra-sim, Mentor design manager tools, VHDL/Verilog, Synopsys Tools, Matlab, OrCad, ADS, MS project

Legal: IP, Patent, Copyright, trademark & trade secret law


Confidential, Chandler, AZ

Product Definition & Application


  • Understand OEM and Tier 1 issues, roadmaps and production cycles
  • Interact with customers and define next generation battery management system requirements
  • Perform market and competitive analysis
  • Review and optimize product cost
  • Develop long-term product road map and marketing strategy
  • Present new products to current and new customers


System Development & Functional Safety


  • Architect automotive semiconductor product to meet ISO 26262 ASIL D requirement
  • Develop product item definition, hazard analysis, functional safety concept, technical safety concept, and verification plan under Automotive SPICE practice
  • Preform chip level DFMEA and Pin FMEA
  • Create and analysis chip level and system level FMEA, FTA for different ASIL requirements
  • Utilizing ASIL decomposition to optimize development cost and time
  • Create safety manual and hardware integration reports to finalize products meet defined ASIL level
  • Provide on-site and off-site customer system level schematic and layout review
  • Support customer to meet different ISO and IEC standard including BCI, ESD, and EFT
  • Review and provide options to lower customers’ BOM cost

Confidential, Tempe, AZ

Product Development and Design Project Lead


  • Interact with customers to define system requirements
  • Manage and execute multiple product developments and introductions concurrently
  • Manage 20+ engineers on design projects and communicate project status to stakeholders
  • Define design methodology to meet high yield and robust product designs
  • Build engineering team, manage and track program schedules, technical issues, priorities, risks assessment and implement risk mitigation plans
  • Engage cross-functional stakeholders for product definition decisions
  • Facilitate communication and collaboration across engineering functions, operations and customer
  • Define and document design tradeoffs for time-to-market introduction, project spec and architect
  • Identify, plan and develop project resources and schedule
  • Optimize product chip size, package cost and test time reduction to meet cost targets
  • Offer multiple levels of status across a wide spectrum of individual contributors to executive management
  • Evaluate and analyze next generation PMIC market strategies
  • Define and drive new IP development for cost effective next generation PMIC and wearable IC architectures
  • Develop and improve IP re-use strategies
  • Define product level FMEA, pin/package FMEA, functional block design FMEA
  • Define system specification and architecture
  • Work with external IP design house vendors and resolve system level integration issues
  • Design low power LDO, multi-phase buck convertors, low power band-gap, voltage and current reference, and temperature monitor
  • Design new ESD structure for secondary protection
  • Create block and chip level simulation/verification plans and methodology
  • Instruct product and test engineers on test time reduction and yield improvement
  • Guide application engineers on reference board design to ensure design win
  • Define and create application system model for EMC, EMI, and DPI requirement
  • Lead Fault Tree Analysis on production issues
  • Mentor & train junior design engineers

Confidential, Menlo Park, CA

Design Lead


  • Lead design & system team on product development
  • Plan & optimize design schedule, layout area, floor plan, pin location definition & cost
  • Design functional blocks: charge pump, low power Op Amp, comparator, voltage & current reference, LDO, voltage regulator, level shifters, filter, I/O & ESD
  • Create robust power-on reset & start-up circuits
  • Design I/O to handle 6-27MHz external square wave clock or sine wave input signal
  • Analyze PSR, cross-coupling effects and devices breakdown to protect circuitries
  • Analyze and characterize new fabrication process device parameter
  • Supervise chip layout to optimize area and minimize noise

Confidential, Fremont, CA

IC Design Lead


  • Communicate with sales, application and system engineers on new and existing products to satisfy customers’ requirements
  • Lead new product specification, monitor and solve CQI and yield issues on 50A high efficiency power management IC and provide work-around to customers
  • Plan design schedule, layout area, floor plans and pin definition to meet the target design cost
  • Create test plans and instruct product/test engineers to optimize test time
  • Design functional blocks: low power Op Amp, Comparator, A/D, Bandgap, voltage & current reference, sample & hold, switch cap, multi-phase buck converter, LDOs, level shifters, filter, I/O and ESD
  • Create overshoot/undershoot detection and power-on reset circuits to achieve robust start-up
  • Design area efficient Complex Darlington BJT to protect loading circuit
  • Analyze PSR, cross-coupling effects and devices breakdown to protect circuitries
  • Supervise low noise & area optimized area chip and PCB layout design
  • Define test parameters, logic and ATE test sequence to reduce test time cost

Confidential, Sunnyvale, CA

IC Design Engineer


  • Design process transferable standard functional blocks: DC boost/bulk converters, PWM driver, comparator, multi-state charge-pump, bandgap, low power oscillator, non-overlap clock and counter
  • Analyze design performance and trade off to optimize chip area
  • Supervise layout and floor plan to minimize routing impedance

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