Chief Technologist Resume

OBJECTIVE:

A challenging position which involves coding a verification environment and/or coding functional verification test benches/tests for a processor/soc design group to ensure fully functional first silicon.

SUMMARY:

Extensive knowledge of ARM, MIPS. Fujitsu, NEC, PowerPC and VLIW Microprocessor architectures
Writing Test benches for Processor Designs and SOC block/system level testing of the RTL in System Verilog, Verilog, VERA, SPECMAN and OVM/UVM, RVM/VMM.
Extensive knowledge of several industry standard interface/bus architectures, including: PCIe, AHB, USB 2.0, DDR, Denali Memories & Digital Video/MPEG.
Extensive Knowledge of FPGA, Emulation, Formal Verification Techniques and Assertion Based Verification in SVA, PSL and OVL
Experience using various Verilog simulators like VCS, Verilog - XL, Finsim etc:
Experience using different Waveform viewers and analyzers like Signalscan and Debussy
Writing complex tests in several Assembly Languages & C/C++ for processor designs & chip level verification.
Verification of Design-For-Test (DFT) features including scan, at-speed test, MBIST, JTAG, I/O loopback and boundary scan for a highly integrated SoC. Responsible for BIST, scan insertion, ATPG and post silicon validation.
Experience developing vectors for ATE validation.
Using test coverage tools like HDLscore to measure RTL code coverage by tests.
Writing Pseudo-Random Directed test pattern generators for processor & SOC designs.
Writing cycle accurate simulators for processor RTL in C
Complex corner cases to test the pipeline and caches and several concurrent events in a microprocessor a strength.
Patent owned for a top down verification process invented at Sony Corporation.

EXPERIENCE:

Confidential

Chief Technologist

Responsibilities:

I am also responsible for ramping up a local team of experienced design verification engineers who are proficient in verification methodologies and to

Confidential

Verification Engineer - Processor & SOC design

Responsibilities:

Working as an independent consultant, responsible for delivering Processor and SOC verification environments at the block level as well as the chip level.
Currently working on a testbench and tests for a cryptographic co processor based SOC in VMM. Also developed an OVM verification environment wrapper for DSP processor.
Developed score boards in OVM/UVM.
Worked on SOCs with DDR & PCIe interface blocks.
Also, wrote and implemented verification environment with tests for a bridge from AXI4/ACE4 ARM 15 to proprietary buses.
Responsibilities include writing System Verilog assertions for key blocks and OVM tests as well as Verilog/System Verilog & Assembly Language chip level tests.

Confidential

Verification Engineer - ARM Processor & SOC Chip Verification

Responsibilities:

Responsible for ARM based mobile phone Confidential SOCs’ verification including block level and chip level test benches and verification in simulation as well as functional formal verification.
Wrote comprehensive test plans, and coded tests at the block level and chip level in System Verilog, assertions in SVA & OVL as well as complex concurrency tests in System Verilog.

Confidential

Verification Engineer

Responsibilities:

Developed assertions in System Verilog and OVL for crucial blocks and designed a fully synthesizable unified test bench that would cover all phases of chip design from block level, chip level, FPGA all the way to emulation and silicon testing..

Confidential

Verification Engineer

Responsibilities:

Responsible for promoting and deploying Confidential ’s Formal verification model checking tool RULEBASE with PSL assertions to key semiconductor houses.
Wrote Sugar/PSL assertion packages - with constraints, for control logic heavy blocks, for various customers.
In addition, lead the verification efforts for a PCIE core.

Confidential

Verification Engineer

Responsibilities:

Entrusted with coding the Architecture Verification tests for most crucial/complex blocks.
Designed and Implemented block level test benches, directed complex diagnostics as well as pseudo-random directed tests to hunt for hard to find corner case bugs.

Confidential

Verification Lead and Manager

Responsibilities:

Implemented the validation/diagnostics strategy for IDT's Cronus MIPS Microprocessor and other communication SOCs, including complex directed tests and Pseudo Random Test programs to ensure fully functional first silicon.
The tests would force several complex events at the same cycle and then make sure that the processor could correctly resolve them and take appropriate actions.

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