SUMMARY

• Over 15 years of professional experience in electronic system and semiconductor hi - tech industry. Strong expertise in product, test development, reliability engineering and device failure analysis for RF mixed-signal, 10/40-Gbps SerDes data/telecom, optical imaging MEMS sensor and memory SOC products.
• Successful track record of leading products through various stages of development, proof of principle, device prototyping, pre-production and overseas mass-production. Goal oriented of completing projects on time. Strong analytical and problem-solving skills, able to resolve technical challenges, and provide creative solutions in high pressure production environments.

PROFESSIONAL EXPERIENCE

Confidential San Jose, CA

Principal Product & Test Engineer

Responsibilities:

• Perform device prototyping, initial silicon bring-up, test program debug, product characterization, qualification stress tests, bench/ATE correlations, establish SPC test limits with JMP statistic tool for wafer sort, final tests, data analysis and products releases to mass-production and oversea manufacturing.
• Drive test characterization plans and test program development on ATE HP93K, Teradyne and LabVIEW test platforms with C++, C#, Python script languages.
• Design for testability implementation and strategies, capability to provide input to design groups to ensure reliable and accurate production testing.
• Develop and implement RF, high speed SerDes networking test methodologies and test hardware interfaces.

Confidential . San Jose, CA

Sr. Staff Product/Test & Reliability Engineer

Responsibilities:

• Drove and executed product, test(HP93k) and reliability qualification developments. Performed device prototyping, product characterization, qualification(JEDEC stress tests), bench/ATE correlations, and products releases to mass-production and oversea manufacturing.
• Led device failure analysis activities for product development and RMA. Collaborated with design, test and application engineers to optimize testability (DFT/DFM), test cost objectives and yield entitlements.
• Collaborated with foundry process engineers in various phases of semiconductor device design, process modeling to develop efficient processes resulting in significant yield improvement and satisfactory reliability.
• Managed customer returns by performing fault localization and root cause analysis. Provided interim/ final reports and corrective/ preventive actions up to customer satisfaction.

Confidential . Santa Clara, CA

Product & Test Engineering Manager Mixed Signal

Responsibilities:

• Led new product developments and managed sustaining mixed-signal/hi-speed SOC digital product activities. Developed ATE test programs and characterized CMOS imaging sensor products on Teradyne, HP93K, and Credence test platforms.
• Oversaw ATE test, wafer process and manufacturing team to resolve testing, processing, and assembly issues.
• Engaged wafer foundries in yield entitlements. Managed yield improvement by identifying root cause of wafer and color filter processing anomaly issues at foundries.
• Drove production cost reduction activities in manufacturing operations. Built strong customer and vendor relationships; interfaced frequently with overseas and local test subcontractors to effectively manage yield, cost, and quality.

Confidential San Jose, CA

Sr. ATE Applications Engineer, Mixed Signal Test Technology

Responsibilities:

• Developed, designed and debugged complete set of customer test solutions, including wafer sort, final test, and characterization programs for fabless semiconductor companies. Converted ATE test programs to various test platforms. Projects focused on RF Mixed Signal, and Hi-speed SOC and CPU/MCU/MPU/GPU/NPU products.
• Provided on-site support to resolve tester software, hardware and test program correlation issues.
• Provided customer training and technical sales support. Held technical seminars and delivered expert consulting services to semiconductor and electronic test engineers.

Confidential, Santa Clara, CA

Mixed Signal Product Test Development Engineer

Responsibilities:

• Designed and developed ATE test software and hardware for RF high speed fiber optics products and maintained wafer sort, final test programs for telecom transceivers, DSL and ISDN products on Teradyne, HP93k and LTX testers.
• Drove and executed DFT/DFM (Design for Testability) logic and fault coverage simulations for VLSI controllability and observability developments. Translated test vectors from design oriented format to ATE format. Improved test coverage by implementing SCAN, BIST, and functional test patterns.
• Performed initial silicon evaluation, product characterization, yield enhancement, failure analysis, and multi-site test program conversion.

TECHNICAL SKILLS

Hardware Test Platforms: Familiar with LabVIEW, C#, Python and ATE test systems: Teradyne-Catalyst, Agilent-HP93K, Credence-Quartet, Advantest-T6672, Next-Test, LTX and Versat-tester. Tektronix/ Lecroy/ Agilent’s digital oscilloscope, I2C bus analyzer, vector signal generators, network and spectrum analyzers, power meters. Expert in ADC, DAC, AMP mix-signal testing with DSP test methodology and test hardware developments with schematic capture tools. Cadence/ Allegro, OrCAD. PCB layout: PADS.

Software and Design Tools: Experience with DFT, ATPG logic fault simulation tools. FPGA, MCU, Firmware programming. Familiar with LabVIEW 8.20, C/C++/systemC, python, Perl, RTOS, Unix, Sun/HP utilities ESL(electronic system level), RTL synthesis with Mentor graphics, Cadence Verilog-XL and Synopsys tools, Primetime and Hspice simulations. Experience with Split corners characterization and process data analysis with JMP statistical software.

Device FA & Qual Techniques: Familiar with FIB, E-Beam/ Pico-probing, Obirch/ Hypervision emission, liquid crystal, de-processing, SEM, TEM, TIVA, EDS and CSAM FA techniques. Experience working with local and off-shore foundry, assembly, qualification and test partners.