SUMMARY:

• Formal Assertion based Verification in Industrial Setting and Methodologies such as Formal and VCS Engine Orchestration, Magellan and JasperGold, programming in System Verilog and Verilog. Hands - on object-oriented verification methodologies UVM and VMM. Key member of an low power ASIC verification team responsible for building random-based block level and chip level test benches for testing RTL blocks and full chip. Solid knowledge of test bench components of drivers, scoreboards, sequencers, monitors, checkers, and integrating C model in score boards using DPI. Generating and debugging random-based high quality tests. Running regressions, debugging failures, generating code coverage reports, improving code coverage, writing and executing test plans. Writing assembly-based or C based firmware tests for verifying the hardware of storage protocols and FLASH memories.
• Generate unique SystemVerilog UVM configurations (SystemVerilog Code) using the Cadence Denali PCI Express Verification IP for several chip level testbenches: architecting testbenches SystemVerilog UVM or OVM
• Expertise on pre-silicon verificationb for low power design methodology development with experience in developing/implementing low power techniques (e.g. power-gating, clock-gating, multi-VDD, body biasing, etc) with real SOC designs verify a DMA engine using UVM with Specman (UVM e)
• Familiarity with PCIe and Ethernet protocols, standard memory models (DDR, eDRAM, etc.), and other network protocols verify memory controllers and FPGA designs; Experience with emulators like Cadence Palladium, Mentor Veloce, or Synopsys Zebu, in both in-circuit emulation and simulation acceleration
• C/C++ development/debugging, including DPI interface to SystemVerilog
• Experience with tools for clock-domain crossing analysis, voltage-domain crossing analysis, HDL lint, assertion generation, register automation
• Expertise with low power rule-checks, equivalence checks and simulation flow with industry leading EDA tools. ( Formality, Conformal LP, MVRC, SpyGlass).
• Experience in low power format standard UPF and CPF developing UVM-based testbenches clock-domain crossing analysis, HDL lint, assertion generation, register automation
• Experience in using current generation MVSIM power-aware simulation tools of Synopsys for high performance IPs, SOCs and VLSI designs.
• Knowing Cadence simulator: mixed-signal verification tools and methodology
• Experience in writing system verilog assertions, specifically for Low power methodology.
• Experience in using VMM/UVM methodologies, Familiarity with emulators, such as Palladium and Veloce.
• •Familiarity with 1) PCIe, RDMA, SR-IOV 2) L1 10G/40G/100G MAC/PCS 3) L2-L3 packet switching/routing 4) Low-latency networking design 5) Memory Controllers 6) SoC's ARM, AXI, PCIe, lpddr2, lpddr3, etc
• SOC design verification for emerging networking products using the latest technologies and having a broad set of skills, from design, to verification, to backend, and hands on lab work.
• RTL Design & Verification Engineer with interfacing of digital blocks to analog circuits experience and have UVM/OVM experience
• Verification lead with 15 years of ASIC and chip SOC/ASIC verification, ASIC, SOC design verification experience Block to chip level verification experience Familiar with verification flow and worked on testbench, testplan, test execution and coverage closure, tape out and silicon validation UVM, VMM, OVM, and familiar with constraint random based verification, including OOP, functional coverage, assertion checker/coverage and virtual interface System Verilog, Verilog, SystemC and Vera Background in Ethernet, PCIe, TCP/IP, Serdes, MAC and PHY Networking IC design and verification, Ethernet switch, PHY, traffic manager, network processor, switch fabric and memory sub system integrating and verifying a SOC design. structural design and optimization flows ranging from Synthesis through GDS and parallel verification flows such as Static Timing Analysis, formal verification, ERC, and power analysis perform design verification on various functional blocks and on the entire system level by developing Verilog and C based SOC firmware tests, and generate test vectors for post-silicon debug and validation structural implementation domain including logic synthesis, physical synthesis, routing, clocks, formal verification, performance verification (static timing), noise, power verification, ERC, reliability verification
• System and Post-Silicon power-up and Validation
• Solid experience in the development of x86 CPU and ARM micro architecture, desktop-specific platform and CPU features, desktop and server-oriented chip set, implementation of point-to-point protocols, multiprocessor memory systems and buses
• Understanding of the interrelationships between CPU architecture, logic design, physical design, system software and hardware, and cost and/or performance
• Knowledgeable Perl scripting and programming language C/C++ development/debugging, including DPI interface to SystemVerilog
• Experience with emulators like Cadence Palladium, Mentor Veloce, in both in-circuit emulation and simulation acceleration
• PhD of Dept of Electrical Engineer & Computer Science, University of California, Berkeley

PROFESSIONAL EXPERIENCE:

Principal Design Verification Consultant

Confidential

Responsibilities:

• Principal Verification Engineer be responsible for defining the test bench environment, generate verification plan and executing the test plan using SystemVerilog for next generation low power Mixed-Signal products; Formal Assertion based Verification in Industrial Setting and Methodologies such as Formal and VCS Engine Orchestration, Magellan and JasperGold, programming in System Verilog and Verilog. Hands-on object-oriented verification methodologies UVM and VMM.
• Analyze, and debug the failures, Write functional coverage: assertions and covergroups Reuse at the system level: UVM agent component and sequences reuse, configuration, initialization architecting testbenches SystemVerilog Language: Assertions, Covergroups, DPI PCI Express Verification IP from Cadence Denali C Cadence eplanner/Vplan Cadence Incisive/ncsim simulator
• Define pre-silicon verification/test plan for next generation low power Mixed-Sigal/SOC products.
• Execute verification plan using SystemVerilog/Verilog using both direct and random test methodology.
• Create and debug test case both in RTL and Gate Level simulation environment.
• Define and generate assertions and functional coverage points. Automate verification environment using Perl and Shell Scripts. Documentation and tracking verification status using coverage matrix and bug tracking system.
• Architect and develop verification environment and testbench components such as BFMs and checkers. Develop comprehensive test plan and implement test cases. Verify design in block and chip level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification. Perform RTL code coverage, assertion coverage, and gate level simulations. verify a DMA engine using UVM with Specman (UVM e)
• Digital Design Verification Lead (UVM/OVM & SystemVerilog) low power CMOS digital design techniques work on functional verification of the RTL associated with datacenter networking, server, and storage systems, advanced power management techniques used by the DSP cores
• ARM, AXI, lpddr2, lpddr3, PCIe, etc Design & Verification low-power verification constrained-random functional verification using System Verilog/Vera Working on the CPF scripts UPF scripts; Verification, using Conformal-LP, that the low-power cells used in the DSP (level shifters, isolation cells, retention flip-flops, power switches) are used correctly. Generation of UPF and CPF models of the DSP. Power-aware simulations of power management sequences at core/subsystem level. Verification of power management strategies for custom array designs Hands-on VMM and UVM synopsys flow for UPF support. low-power design and verification techniques, and in particular, of the concepts supported by the UPF/CPF languages. UPF-based synthesis and implementation using Design Compiler and ICC. Conformal-LP. power-aware simulation tools from Mentor, Synopsys MVSIM BFM simulation to enter and exit L12 substate. PCIE4.0 test. UPF flow MVSIM Synopsys. Design the PMIC block R4 DSM and BFM simulation test case to test the complete power down mode. Simulate this sequence: Power down, R4 wakes up, Copy firmware from LPDDR3 to its ITCM, R4 reboots.
• Create verification plans for complex SOCs and IP blocks
• Develop CPF/UPF script for the SoC Help verification/design/back end team to run low power simulation in RTL using cadence/synopsys simulator. Understand and perform block & chip-level power analysis. Understand and create block-level power models.
• Create testbenches in SystemVerilog/UVM: development of OVM, UVM, VMM and/or C++, Verilog, SystemVerilog test benches and usage of simulation tools/debug environments, to test memory controllers, full chip FPGA fabric and SOCs verify memory controllers and FPGA designs
• DDR3/DDR4 memory controller
• High speed network or switching controller
• Flash Memory or SSD controller
• SATA/PCI-E controller verification
• SOC with embedded ARM processer
• PC chipset, North/South Bridge controller design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of FPGA fabric and SOC designs
• Utilize advanced verification techniques
• Write tools and scripts in Perl
• SoC level with ARM C code
• Good software skills in C++, Visual Basic and Perl Good problem solving and debugging
• SystemVerilog/UVM, OVM and VMM adopting advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
• Domain expertise in PCIe and Low Power PCIe 4.0 L0, L11 and L12
• Using git tools for regression management, configuration management and bug tracking hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, RTL designers, firmware, emulation and verification teams
• Develop UVM-based test benches and test cases based on the test plan Debug test failures at block, full chip, and system level and file bug reports Validate bug fixes from the design team and close bugs accordingly Generate code coverage metrics and analyze the numbers Evaluate and enhance test plans to increase test and code coverage Run regressions and debug failures Develop Firmware based tests to verify chip level blocks Train and mentor junior engineers within the verification team Run gate level simulations with unit delay and SDF timing annotations Verify test logic and DFT circuits including BIST and JTAG logic

Principal Engineer

Confidential

Responsibilities:

• defining, implementing, verifying, and taping out digital designs: specification, verification and validation plans, RTL implementation, coverage driven verification environment implementation and closure, driving the backend to tape out, and lab bring-up;
• Formal Assertion based Verification in Industrial Setting and Methodologies such as Formal and VCS Engine Orchestration, Magellan and JasperGold, programming in System Verilog and Verilog. Hands-on object-oriented verification methodologies UVM and VMM. hands on digital design and verification role - from design, to verification, to backend, and hands on lab work verification architect, establishing the verification methodology, tools and infrastructure for memory controllers, high performance FPGAs, SOCs and VLSI designs working with chip lead to define the digital macro requirements
• Working with analog and digital teammates to define digital block specifications defining microarchitecture
• Verilog RTL design implementation and integration •
• Defining and owning the digital testplan implementing SystemVerilog RTL
• Implementing whitebox coverage and checks using SystemVerilog Assertions (SVA) implementing UVM Verification environment
• Architecting and building digital verification environments SystemVerilog with UVM DV and debug
• Building required directed testcases, Functional coverage implementation, analysis and closure working with chip lead to integrate in different phases of ASIC and/or full custom chip development working with backend house to generate GDS2 synthesis closure (warning free log / cell area requirements met) timing closure
• Define synthesis and backend timing and placement requirements post backend gatesim
• Work with backend engineers to meet area, power, timing, and test coverage requirementsSDF annotated gatesims of both functional and test modes
• UVM/OVM and VMM state of the art of verification techniques, including assertion and metric-driven verification gate level simulation, power verification, reset verification, contention checking, abstraction techniques formal property checking tools Cadence (IEV), Jasper and Synopsys (Magellan)
• Interfaced Digital Blocks to Analog Circuits
• Extensive Verilog RTL Design
• Digital Design
• Verification verification management tools as well as database management for regression management
• Verilog RTL gate-level functional verification and execute regression tests
• Digital testplan Perform design debug and modification using SystemVerilog/Verilog
• FPGAs FPGA programming and software
• Drivers: Building FPGAs for driver development platform
• Lab bringup using validation plan
• Random and constrained random-verification, design for simplicity, design for verification, design for debug, and design for ECO techniques design verification infrastructure and process improvement designing, implementing, and verifying serial host interfaces (RFFE, I2C, SPI) Develop Bus Functional Model and develop test cases synthesis and backend flow, defining SDF constraints, ATPG / SCAN and improve ATPG coverage functional verification tools and methodology for Low Power verification and verifying mixed signal IC; assertion writing and formal verification developing verification components, large verification environments and tests for complex blocks, verifying integrated circuits of mixed signal circuits with VerilogAMS real number modeling for analog circuit behavioral modeling such as DACs, ADCs, switch mode power supplies, phaselock loops, CODECs revision control environments, git, ClearCase
• Maintain tools and tool flow - including a mix of perl and python scripts digital and analog design and hands-on debug of ASIC/FPGA-based systems. verification languages SystemVerilog, Verilog/VHDL
• RTL implementation of memory controllers, clock generation, and various industry protocols such as SDR, DDR, MMC, USB and ATA.
• Driving the verification environment architectureb. Creating test scenarios(System Verilog OVM)c. Work with RTL teams to debug verification failuresd. Review and ensure that expected Code and functional coverage metrics are achieved synthesis (Design Compiler/RTL Compiler) and Timing analysis (Primetime).
• PERL scripting, assembly/C code debugging.
• Hand-on design in the low-power, low cost data-conversion & PLL systems, continuous-time and switched-cap Sigma-delta ADC designs, pipelined ADCs, high-performance Frac-N PLLs, analog baseband circuits of Variable-gain amplifiers, continuous-time filters, LDOs, bandgap bias, op amps, bias generators, bandgap references, regulators, switched capacitor circuits circuit level simulation, schematic entry, layout, and Matlab/Simulink