SUMMARY:

• 22+ years of experience in design and verification involving ASICs, IPs, Microprocessors and SoCs.
• Performed whole verification life cycle from RTL verification to post silicon validation.
• Expert in test plan development, test bench development, project management.
• Expert at behavioral models development, regression management, random testing and coverage analysis.
• Excellent debugging and analyzing skills.
• Good Design Experience.
• Expert in developing random generators and automatic checking and CSH scripting.
• Experienced in SoC verification using C, Vera/NTB.
• Strong at defining the complete verification methodology for Microprocessors, SOCs and IPs.
• Strong verification Experience in AHB MLM, ONFI Host, Hyper Transport Tunnel/Cave, Controller Area Network (CAN), USB 1.1, PCI, SATA, PCIe, AGP, I2C, DMA, SDRAM/SRAM/FLASH & Sparc Microprocessor.
• Expert in Verilog, System Verilog, V2K, SystemC, VPI, VERA, Specman and Test Builder.
• Experienced in VCS, Verilog - XL, ModelSim and Covermeter.
• Expert in RTL and Gate level debugging. Experience in FPGA validation.
• Knowledge of verification methodologies UVM and AVM.
• Knowledge of various debuggers, DVE, Debussy and Virsim.
• Experienced with NCSIM and VCS.
• Good at Assembly language programming for Microprocessor verification.
• Good experience in EDA tool (VCS) validation and customer support.

PROFESSIONAL EXPERIENCE:

Confidential

Responsibilities:

• Developed fullchip test bench. Libconfig is the major tool.
• Verified SMMU at fullchip level.
• Developed fullchip environment to test PCIe.
• Validated and Supported Palladium (Emulation).
• Verified Write Cache Unit (A L2 Cache) at module level. Developed test plan, built cache snoop model.
• Enhanced/Fixed MOESI compliant Level 1 Cache model for Level 2.

Confidential

Responsibilities:

• Designed and Validated Testmode logic for IPUF2.
• Developed SystemC Model. Developed Test Plan. Managed whole delivery flow. Interacted closely with the customer.
• Designed, verified and Validated SHA3 (Keccak) block from scratch.
• Perfomed whole validation on Virtex 5 FPGA and Kintex 7 FPGA. Brought-up Kintex EVB from scratch for Linux and Windows.

Security Controller

Confidential

Responsibilities:

• Architected/Designed/Validated SPI interface.
• Developed complete versatile verification for PUF.
• Performed FPGA validation on Kintex7 bear board and ML501, SP606 EVBs. Setup automatics flow in Linux and windows.
• Designed NFC(Near Field Communication) Controller. Designed SPI interface and DMA interface. Developed SystemC based BFM for PUF(Physical Unclonable Function) IP.
• Developed test plan, verification environment and verified full chip. (RTL and GLS).
• Created UVM based environment for testing SPI I/F.

Confidential

Staff Verification Engineer

Responsibilities:

• Verification Lead for the Project. Lead a team of 9 Engineers.
• Developed Verification strategy, Schedule and Test Plan. Interacted closely with Program Manager, Project lead to meet project goals.
• Executed all the phases of Project, RTL/GLS Validation, FPGA RTL/GLS/Board Testing, ROM Verification, Test Vectors Development and Conformal Verification.
• Involved in developing/debugging/maintaining of legacy and new testing.
• Successfully handled many change requests and dynamics in the project and executed the project meeting project schedule.
• Worked closely with 3 teams in US, India and Israel.

Confidential

Sr. Verification Engineer

Responsibilities:

• Developed verification environment for Confidential JTAG I/F.
• Developed test cases to verify MLM AHB, CPU and Test Mode Controller.
• Involved in debugging/maintaining of many test cases both in RTL and GLS.
• Developed script to analyze/extract unique violations from GLS Logs.
• Generated production test vectors/patterns using Wave Wizard for few tests.
• Designed ONFI 2.3 Host BFM.
• Defined complete verification flow using different vendor’s memory models and different operating modes in which ONFI can work. The whole verification flow has been automated using Perl.
• Developed ONFI 2.3 test plan and wrote test cases.
• Verified PCIe Switch fabric, End point and Root Complex.
• Wrote test cases for PCIe Switch verification and developed compliance suite.
• Reviewed the existing test plan and added additional tests.

Confidential

Customer Support

Responsibilities:

• Supported VCS, DVE and LEDA and ArchPro Low Power tools.
• Performed all customer support related tasks like receiving cases, validating them.
• Suggested workarounds for many customer issues. Created smaller test cases for many customer issues.
• Handled complete save/restore and SDF related issues as a knowledge expert of save/restore and SDF technologies.
• Verified typical debugging flow on DVE. Developed test cases for verification of DVE and LEDA.
• Developed a flow using Perl which can be used to automatically check a test case across all different Confidential releases.

Confidential

Sr. Verification Engineer

Responsibilities:

• Designed and verified Cable Card I/F, PCI and Generic Host I/F.
• Lead a team of 3 engineers to verify PCI and Generic Host I/F. Defined the whole verification for Unit/module/system level testing.
• Developed random generator for PCI/AHB and automated whole checking/execution using Perl.
• Developed the test plan and test cases to verify the PCI and generic Host I/F.
• Developed System level test cases in C for Broadband Modem SoC.
• Assisted in post silicon validation of the whole SoC from bootup to testing application.

Confidential

Sr. Verification Engineer

Responsibilities:

• Verified HT block. Verified FrCPU DMA Engine.
• Developed ToCPU and FrCPU DMA engines in Vera.
• Wrote verification suite in Verilog and Vera and performed regression.

Confidential

Sr. Verification Engineer

Responsibilities:

• Verified System Verilog, NTB/VERA technologies in VCS. Prepared test plans and developed test cases.
• Lead verification of UCLI and VPI technologies in VCS.

Confidential

Technical Lead, CAN, HT Verification

Responsibilities:

• Designed and verified Micro controller I/F for PDIUSBD12 to bridge CAN and USB.
• Lead team to verify/validate CAN controller. Developed test plan and test environment.
• Tested CAN controller on FPGA.
• Designed and verified CAN/RS232 Bridge.
• Verified HT Tunnel and Cave in forward direction.
• Developed Self Checking Verification Environment for HT Verification. Wrote test plan and test cases.
• Assisted testing HT on FPGA.

Confidential

Sr. Verification Engineer

Responsibilities:

• Managed the entire verification related activity for USB 1.1.
• Interacted with vendor and Integrated bus functional models with the system environment.
• Prepared test plan, arranged reviews.
• Wrote several test cases and ran test vectors in Verilog and C.
• Created a C based random generator which reads input file, generates test cases, does automatic checking and reports statistics at the end.
• Maintained Clock Controller Logic test cases.

Confidential

Sr. Verification Engineer

Responsibilities:

• Wrote scripts to automate the random generator running process on system model.
• Ran the random test generator to generate many test cases and debugged failures.
• Wrote targeted corner test cases for I/D cache debug registers and maintained I/D cache and MMU test cases.
• Wrote test plan for SDRAM/SRAM/FLASH Memory controller and memory arbiter.
• Wrote several tests in standalone (Verilog) and System environment (Mips assembly).
• Verified the Memory controller and memory arbiter using Verilog and VERA.
• Wrote test plans for DMA and I2C modules.
• Developed test cases in MIPS assembly language and VERA to verify the DMA controller and I2C.
• Wrote I2C behavioral model and monitor in Verilog for verification.
• Led a team of 4 verification engineers to verify BlueNile ASIC.
• Complete verification of Blue Nile chip that includes development of test plan & test vectors. VERA language used to write the test suites.
• Development of complete system level random generator involving concurrent transactions PCI, CPU, SDRAM, DMA with many random techniques in VERA.
• Developed DMA Controller test plan and test cases in VERA.
• Ran coverage for complete chip in Vericov and developed corner case tests by analyzing the coverage result.
• Validated Confidential 6.1. Developed and debugged many test cases to validate VCS.
• Ran bench mark designs on Confidential 6.1 Pre Alpha and developed/maintained bench mark test cases to validate VCS.
• Resolved customer issues.

Confidential

Verification Engineer

Responsibilities:

• Developed test plans for PCI Target, DMU (DMA Monitoring Unit) and SPDIF Controller.
• Developed PCI 2.1 Compliance test suite and automated test bench.
• Developed PCI Monitor, AGP Monitor and transaction generator and tested PCI Master/Target Models, AGP Core.
• Developed regression test suit and automated whole regression checking.
• Designed CFG/CSR logic, I2C Bus interface, Synchronization logic for PCI target.
• Developed SBA (Side Band Address) Logic, Q-logic and Target-Host interface in AGP Master Simulation Model.
• Wrote diagnostics for a LAN-WAN interface card.
• Tested mother board and line cards for EPABX.