PROFESSIONAL SUMMARY:

• ASIC Design Engineer with 15 years of experience in all phases of SoC/ASIC product development cycle.
• Core member of product development and integration teams with history of successfully delivering more than 15 semiconductor SOCs with design complexity of multi - million gates for technology nodes from 10 to 80nm.
• Experienced in high-speed/low-power complex ASIC design, architecture and verification.
• Designs developed include clock/reset/power controls and video/graphics/display technologies from specification to design to bring-up.
• and participate in regular design and documentation reviews.
• Successfully led integration of complete multi-media sub-system involving multiple cross-functional IP development teams from multiple global sites.
• IPs integrated also includes Analog IPs such as PLL, PHY, DAC, Droop Detector. Strong aptitude for building long term relationship with various stakeholders
• Extensive knowledge in Synthesis, STA, Formal Verification, Confidential, PLDRC, Low Power checks.

SKILLS:

HDL: Verilog, VHDL

Simulation & Debugging Tools: ModelSim, VCS, NCSim, Verdi, DDD

Synthesis: Synopsys DC, DCG, DCT

Formal Verification Synopsys: Formality, Cadence Conformal

DRC: Checking Atrenta SpyGlass, Mentor 0-in

Static: Timing Analysis Synopsys Prime Time, GoldTime

Low Power Design Synopsys: Power Compiler, VC LP, CPF/UPF, Encounter CLP

Revision Control: s/w ClearCase, ClearQuest, JIRA, RCS, Perforce, CVS, SVN

Acquired Knowledge System: Verilog, UVM, C

Protocol Knowledge: AMBA-AXI, AHB, APB buses

Scripting Language: TCL

Documentation Tools: Visio, Frame Maker, MS Word, PowerPoint, Excel

OS: Familiarity Linux, Unix, Windows

PROFESSIONAL EXPERIENCE:

Confidential

Senior Staff ASIC Design Engineer

Responsibilities:

• Core member of MultiMedia development and integration team. Responsible for architecture and design of clock, reset and power controls to multimedia cores such as camera, display, video and graphics. Develop technical diagrams and hardware programing guide for clock block used by Verification, SW and FW teams.
• Reduced clock block area by 15%. Achieved this by reducing number of PLLs by re-configuring VCO frequencies, sharing and re-allocating PLL assignment to the cores and enabling PLL low jitter mode. Provided new solutions to overcome the shortfall and establish handshake between few in-house clock library modules.
• Co-inventor of in-house invention “Hardware controlled memory inrush current management scheme”
• Work closely with Verification team during RTL, Power Aware and Gate Sim. During chip bring up helped SW team to debug a complex chip hang issue related with clock/power sequence. Provided a workaround solution resulting in preventing schedule delay in an accelerated time-to-market project timeline.
• Led architecture and design of effuse based Frequency Limiter feature that avoids unauthorized overclocking above a threshold clock frequency. This resulted in marketing differentiator among various tiers and leverage product pricing while using common silicon.
• Took ownership for architecture/design/documentation of Danger Safe Aggregator and Throttle (DSAT) IP for bandwidth management of real-time and non-real-time DDR clients.
• Integration lead for MultiMedia Sub-system working closely with IP, SoC and Implementation/PD teams across multiple sites. Managing releases, Confidential /PLDRC design rule checks, ECOs, timing closure, documentation. In recognition of flawless execution, promoted in less than 2 years of hiring.

Confidential

Principal ASIC Design Engineer

Responsibilities:

• Owned architecture and design of IPs such as Video Image Sharpening Processor, Local Adaptive Contrast Enhancement, Super Resolution, sub-modules of 2Dto3D Conversion, 3D Depth Control and memory controller interface as a core member of Digital TV (DTV) and set-top box IP development team.
• Developed I2C master-slave protocol logic to connect to an off chip low speed peripheral.
• Worked closely with core and chip level Verification teams during various phases of design cycle such as RTL, mixed Gate sim, pre/post unit-mint/maxt Gate sim, Palladium/Veloce sim. Developed a new mixed Gate-sim flow that helped expedite validation of IP at integration level.
• Optimized design by utilizing innovative implementation method which reduced block area by more than one third. Detected QoR bug in Synopsys DC and worked closely with Synopsys FAE to resolve it.
• Synthesized blocks during early design development phase to find out any potential timing, area and routing /congestion issues. Led constraint generation, synthesis, Formal Verification, STA for 2 layout blocks and worked with PD/design teams across multiple global sites on clocking, routing/congestion, constraints and timing closure issues. Managed netlist transfer between PD and core teams for ECOs.
• Close involvement in inter-department deliverables, communications, design-guidelines. In recognition of excellent multi-tasking skills and strong work ethics was promoted after 2 years.

Confidential

MTS ASIC Design Engineer

Responsibilities:

• Developed RTL (starting from C model algorithms) for motion estimation and motion compensation video processing IPs. Executed Design Verification, Formal Verification, DRC checks and synthesis for this IPs.
• Provided tape-out support during critical deadlines and worked under intense project schedule to fulfill end customer product launch requirements.
• Lead for display sub-system layout block. Responsibilities included constraints generation, synthesis, Formality, STA, interacting with PD on CTS, congestion/routing, constraints and timing closure issues and netlist signoff. Managed netlist transfer between PD and display core team for ECOs.

Confidential

ASIC Design Engineer

Responsibilities:

• Spearheaded design for graphics scaler (pipeline and control) and hardware cursor, advanced de-interlacing, interrupts and crc RTL functional blocks. Design verification/validation using DDD, pre/post/timing sim, DRC check, Formality.
• Owned display sub-system integration and synthesis. Worked closely with display team assisting in resolving various tool flow issues, constraint issues, complex functional ECOs and netlist signoff. Avoided complete spin by implementing a complex functional ECO for a last minute change request.