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Sr. Asic Design Verification Engineer Resume

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Sunnyvale, CA

OBJECTIVE:

Seeking for ASIC Design Verification Engineer Position.

SUMMARY:

  • Experience with Gate level simulation with SDF and debugging.
  • Experience with Regression and Triage.
  • Experience with Ethernet and XAUI(10GBase - T)
  • Experience with ARM based SOC structure and AMBA bus.
  • Experience with DDR2/DDR3, PCIE, I2C and SPI interface
  • Experience with Synopsys s Synthesis and PrimeTime tool.
  • Experience with Digital IC design.
  • Experience with Xilinx FPGA design and synthesis tool .
  • Experience with Verilog RTL level coding and simulation.
  • Experience with Modelsim.and Synopsys VCS Experience with TCL and Perl coding.
  • Experience with C & C++ language.
  • Experience with SystemVerilog and OVM/UVM methodologies
  • Experience with BFM, checker etc. development
  • Experience with directed and random constrained generation
  • Experience with Code coverage and assertion base verification
  • Experience with Pre-Silicon verification and Post-Silicon validation
  • Knowledge of Cache Coherency Knowledge of SATA

EXPERIENCE:

Confidential, Sunnyvale, CA

Sr. ASIC Design Verification Engineer

Responsibilities:

  • Working on UVM test environment.
  • Write testcases to verify DMA functions, power management functions, I2S slave functions, and EFUSE functions.
  • Gate-level simulation and Debugging.
  • Generate test vectors for ATE.

Confidential

Sr. ASIC Design Engineer

Responsibilities:

  • Perform logic synthesis and timing analysis help to port OVM environment to UVM test environment whole chip verification

Confidential, Mountain View, CA

Design Verification Engineer

Responsibilities:

  • Pre-Silicon Verification Verify I2C, JTAG, and EFUSE blocks Write Systemverilog to create new testcases in UVM environment help with testbench build-up Use Systemverilog to write new functions/tasks to verify RTL new features in UVM environment
  • Run assertion-based simulation to verify RTL design and debug
  • Run code and functional coverage and increase code coverage rate by writing new tests
  • Perform full Chip and Gate-level SDF verification
  • Perform regression Use Matlab for post-silicon chip bringup validation.

Confidential, San Jose, CA

Design Verfication Engineer

Responsibilities:

  • Build up UVM verification environment
  • Use Systemverilog to write new functions/tasks in UVM environment Verify and Debug for TV-Decoder SOC project develop test plan
  • Verification environment built-up Integrate Microprocessor, AMBA bus, PCIE, DDR2, SATA, TV-Decoder and Run simulation

Confidential, Sunnyvale, CA

Senior ASIC Design/Verification Engineer

Responsibilities:

  • Run whole chip verification and debug for network processing project
  • SOC top level verification environment built up and generated testcases SOC chip level simulation and verification for SOC project
  • Assertion and random test generation Gate-level ECO fixing Revision control and bug tracking by using svn Xilinx FPGA design validation and debug modify and import RTL design to FPGA, and generate FPGA bit stream. verified paths from ARM processor to network processor IP, and paths between Gbit Ethernet, PCIE, memory and network processor IP. Design RLDRAM memory controller
  • Design I2C master block
  • Design SPI interface
  • Design GPIO and MDIO blocks
  • Design Packet-Dropped-Count Engine block
  • Integrate XAUI block ( IP from K Micro)
  • Integrate XGXS block ( IP from Mentor Graphics )
  • Run Synthesis and Primetime AMBA AXI Bus evaluation and integration for ARM based SOC project
  • Perform post-silicon validation

Confidential, Mountain View, CA

Senior ASIC Design Engineer

Responsibilities:

  • Pre - Silicon Verification Implement NTSC443 and PAL60 features into IP design.
  • Design RGB to YCbCr converter.
  • FIR filter implementation
  • Video Decoder IP codes study and verify.
  • Write I2C model to verify Decoder s Registers function.
  • Build up simulation environments and write test cases to verify functional blocks.
  • Perform logic synthesis and timing analysis
  • Design CCIR656 encoder.
  • Gate-level ECO fixing
  • Micro-architecture of functional blocks.

Confidential, Fremont, CA

Senior ASIC Design Engineer

Responsibilities:

  • Pre - Silicon Verification
  • Design T3/E3 framer as a company's IP and target for OC12 to OC48 data rate.
  • Debug and implement new features for SONET project.
  • Gate-level/ECO fixing.
  • Generate test vectors.
  • Perform logic synthesis and timing analysis

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