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Staff Design And Verification Engineer Resume

Fremont, CA

SUMMARY:

A highly efficient, hardworking design engineer with a comprehensive understanding of SoC design processes.Experienced in most of design stages of a product, including Architecture studies and developments, RTL coding, TestBench development and verification, Synthesis, Formality checking, ATPG generation and simulation, MBIST generationand simulation, Static Timing Analysis, and ATE debugging. Possessing a good team spirit and a deadline oriented individual. Keen to find a challenging and suitable engineering position with an ambitious company that offers opportunities forcareer development and advancement.

SUMMARY OF SKILLS:

Synopsys HDL Design Tools (Design Compiler,Cadence HDL Design Tool (NC Verilog)Primetime, Formality, ATPG, VCS)Verilog HDLXilinx/Altera FPGA toolsSystem Verilog with VMMSynopsys Debugging Tools (Debussy, Verdi, nLint)Script Tcl, PerlMentor Graphic MBIST (Certified of Completion ofTessent MemoryBIST and LogicBIST)

EXPERIENCE:

Staff Design and Verification Engineer

Confidential, Fremont, CA

Responsibilities:

  • Main duties include micro - architecture, HDL design LPC SlaveInterface based on the Intel LPC and Serial IRQ specification.
  • Verifed LPC Slave Interface design by using theUART System Verilog with VMM Verification IP.
  • Ported full design onto Altera FPGA platform for system level verification.
  • Signed off Logic Synthesis and Statics Timing Analysis.
  • Worked on various USB UART projects. Main duties include signed off Logic Synthesis, Synopsys ATPG vector generation and simulation, Mentor Graphic MBIST vector generation and simulation, Synopsys Formaltiy verification, Statics Timing Analysis and created System Verilog Verification tasks to verify OTP (One TimeProgramming) memory.Supported Mentor Graphic MBIST vector generation and simulation for a 24 Million gatesCompressed/Decompressed Security Engine chip.
  • Worked on OTN (Optical Transport Network) project. Main duties include HDL design and verify SFI4.2(SERDES Framer Interface Level 4 Phase 2), which is an interface for aggregate data bandwidths of OC- 192and Packet over SONET/SDH (POS), as well as other applications at the 10 Gb/s data rate.
  • Verified ODU0 (thesmallest OTN container, operating at 1.25 Gbps.)Designed/Verified SONET transmitter for FPGA SONET chip verification.
  • Ported the design onto Xilinx FPGAplatform to verify bug fixes in SONET Receiver.Worked on various T1/E1, T3/E3 chips.
  • Main duties include implemented new features from customers, verifiedthese new features, and signed off full chip Logic Synthesis, and Static Timing Analysis.Worked on SONET chip.
  • Main duty include verified VCAT (Virtual Concatenation) with LCAS (Link CapacityAdjustment) in the existing Verilog Test Bench.

Senior Logic/ASIC Design Engineer

Confidential, San Jose, CA

Responsibilities:

  • Designed Power Control and Data Path in 32-bit ARM compatible Embedded Microprocessor Core (high performance and low power) with a strong understanding of CPU Micro Architecture and Pipeline design usingARM9TDMI Instruction Set.
  • Verified all designs by using Vera Random Package generator at block level and VSG (Vera Stream Generator)at system-level to generate assembly code tests.
  • Implemented test environment for 3 MACs and 4-port Switch byusing Flexmodel Transmitter and Receiver from Synopsys with good understanding of Ethernet System protocolspecification.
  • Designed/Verified AHB Slave interface and Test Environment for Public Key Engine and Random NumberGenerator for a Network Processor.
  • Designed I2C Master Controller, which provided a simple bi-directional 2-wire bus for efficient inter-IC controland multi operation through arbitration with synchronized clocks in a highly integrated SOC, which functioned asa central block for cost-effective, high performance/low power systems.

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