SUMMARY:

My objective is to find a company that will utilize my hardware design skills/experience and provide me with a challenge beyond my current expertise level.

SKILL:

Hardware: Confidential, Altera, Actel, Lattice, Motorola/Intel Processors, PCI, cPCI, PMC, ATCA, AMC, USB, PCMCIA, SPI, Motor Control, DDR/DDR2/DDR3 SDRAM, SRIO, SERDES, AXI

Software: Confidential /Altera/Actel/Lattice Confidential Design Tools, Mentor Graphics, Synopsys, ModelSim/QuestaSim, Synplicity, Aldec Active - HDL, VCS, Interconnectix, Spice, MATLAB, OrCAD, ViewLogic

Languages: VHDL, Verilog, C/C++, OrCAD HDL, Assembly, Ksh, Perl, Tcl

Operating Systems: UNIX (Solaris, HP), MS-Windows, Linux

EMPLOYMENT:

Confidential, Milwaukee, WI

Verification Engineer

Responsibilities:

• Was responsible for the verification of various Confidential Series 7 FPGAs designed for a naval power distribution system.
• Created VHDL testbenches and bus functional models (BFMs) for verification purposes.
• ModelSim DE was used for design verification.

Confidential, Fort Worth, TX

Design Engineer

Responsibilities:

• Was responsible for designing and implementing Lattice FPGAs, using VHDL, for use within commercial avionic control systems.
• The Confidential was used to provide motor control and monitoring of all primary flight controls by using pilot/co - pilot selections as well as flight control feedback loops.
• Was required to follow the DO-254 Confidential design process.
• Lattice Diamond was used for Lattice Confidential implementation, QuestaSim for design/verification and Synplify Pro for synthesis.

Confidential, Alpharetta, GA

Verification Engineer

Responsibilities:

• Was responsible with the verification of Confidential IP for DO-254 compliance.
• The Confidential IP being verified was AXI-based for use within Confidential Embedded Design Kit ( Confidential ).
• Followed the DO-254 hardware verification process for IP verification that included creating IP design requirements, creating a test plan to verify those requirements, designing VHDL/Verilog models/testbenches for simulation test environment and creating test cases that followed/verified the created test plan.
• The Confidential IP verification for DO-254 compliance was done in both simulation and lab environments.

Confidential, Dulles, VA

Design Engineer

Responsibilities:

• Was responsible for designing and implementing Confidential FPGAs, in VHDL, for space satellite applications.
• Worked mainly on the next generation Command and Data Handling (C&DH) satellite subsystem.
• Some of the functions that were implemented were a proprietary serial communications bus for inter- Confidential communication, A/D data control/collection, data packetizing and memory interfacing. Confidential Designer 9.1 was used for Confidential implementation, Aldec Active-HDL for VHDL design/verification and Synplify Pro for synthesis.

Confidential, Centennial, CO

Design Engineer

Responsibilities:

• Was responsible for designing and implementing FPGAs, in VHDL/Verilog, for aerospace data storage and processing solutions as follows:
• Designed various functional logic blocks, in Verilog, for a solid-state recorder system. The Confidential Virtex-5/SIRF device was used for logic implementation and built using ISE 12.3. The logic blocks were designed around a Confidential internal switch fabric that interfaced to several serial RapidIO (SRIO) ports, SERDES control logic to/from other Confidential devices, Confidential internal control/status and built-in self-test (BIST). The system dataflow was controlled using router logic within the Confidential that allowed data storage to/from various memory storage cards. A SystemVerilog testbench was used to simulate and verify the Confidential and system dataflow using QuestaSim.
• Worked on a communications satellite processing subsystem. Designed and implemented a Confidential Virtex-6 device for a test card that would be used for various dataflow test methods. The Confidential was designed using Confidential 13.1 and contained a mixture of Confidential library logic and commercial/custom IP. The various data interfaces implemented for dataflow included PCIe, DDR3, I2C, GPIO, SERDES and Ethernet. The main logic was designed using Verilog, although the design did have a mixture of VHDL/Verilog. Also designed a custom DDR interface controller for the communications processing system using Verilog and was to be used in a Virtex-5/SIRF device.

Confidential, PA

Design Engineer

Responsibilities:

• Was responsible for designing and implementing FPGAs, in VHDL, for a 8-channel optical multi-gigabit data accumulator/mapping card.
• There were 2 Confidential Virtex-II Pro FPGAs used for the multiplexer/de-multiplexer data transfer architecture.
• The multiplexer Confidential multiplexes up to eight serial streams, from the 8-channel RocketIO interface, of various types/rates into a single composite bit stream of approximately 9.42 Gbps. The de-multiplexer Confidential reverses the multiplexer Confidential mapping by de-multiplexing a single composite stream into up to eight serial streams.
• The de-multiplexer Confidential also had two independent modules of 2GB DDR2 SDRAM for recording received data traffic. Both FPGAs interfaced with a PowerQUICC II for processor applications. A Confidential Virtex-5 FXT device was later used to upgrade both FPGAs performance/flexibility.
• Confidential ISE 9.2/11.5 was used for Confidential implementation, ModelsimPE for verification and XST for synthesis.

Confidential, Hartford, CT

Design Engineer

Responsibilities:

• Was responsible for designing and implementing FPGAs, in VHDL, for an industrial inkjet printer product. Several Confidential Spartan-3E FPGAs were used to implement print data control logic along with printer electrical control interfaces.
• The print data control logic functional blocks included a source-synchronous serial I/F, PowerQUICC III Microprocessor (PCI, Local Bus) I/F, Confidential USB AVR Microcontroller (8051) I/F and pixel data formatting/flow-control
• The main printer electrical control functions implemented were motor control (Stepper, Servo, DC), Delta-Sigma ADC/DAC for printhead heater/power control and internal timer/interrupt controllers.
• Confidential ISE was used for Confidential implementation, ModelsimPE for verification and XST for synthesis.

Confidential, San Diego, CA

Design Engineer

Responsibilities:

• Was responsible for designing and implementing FPGAs, in VHDL/Verilog, for use on a CDMA-functional development platform.
• Work involved parsing ASIC Verilog code across multiple Confidential Virtex-4 FPGAs, which allowed for chip verification and early software development.
• The Confidential code development was a mixture of VHDL/Verilog wrappers and included chip-level functional parsing, clock synthesis/distribution, reset control and high-speed inter- Confidential communication modules.
• Confidential ISE, along with Chipscope Pro, was used for Confidential implementation/verification and Synplify Pro for synthesis.

Confidential, Dallas, TX

Design Engineer

Responsibilities:

• Was responsible for designing and implementing FPGAs, in VHDL, for use within WiMAX products. These products were part of the next generation in wireless broadband. The functions implemented were based on switch-fabric architecture between the Confidential and one or several TI OMAP5912 application processors within WiMAX base stations and PCMCIA-based modem cards. Confidential ISE was used for the high-density Virtex-4 and Spartan-3E Confidential implementation and ModelsimPE was used for design verification.