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Staff Cad Engineer Resume

Santa Clara, CA

SUMMARY:

Seasoned CAD engineer with a passion for well written, maintainable code and clean user environments. Time off, but I’m keeping my linux and software skills up - to-date with online course work.

PROFESSIONAL EXPERIENCE:

Confidential, Santa Clara, CA

Staff CAD Engineer

Responsibilities:

  • Developed a comprehensive set of standard cell layout checks to reduce iterations between the layout and physical design teams.
  • Checks were written using Calibre DRC and Cadence PVS.
  • Built a browser based, Skill code linter providing a refined view of the linter output while also pulling in data from the source code repository (like who checked in a file with a bunch of errors). Web pages were generated by a Python script that emitted HTML and JavaScript (with jQuery).
  • Also setup and maintained the Jenkins server that launched the linter and the nginx web server the application ran on.
  • Administration of design data management system (ClioSoft) and FlexLM license servers.
  • User support for Confidential software.
  • Liaised with tools vendors for bug resolution and workarounds. Setup, administered, and contributed to Wiki-based documentation.
  • JavaScript, HTML, Perl, Python and MySQL development for an in-house, LAMP stack, interactive digital test plan development and design verification tool.
  • Developed a Skill language standard cell abstract generator (output in LEF) integrated with Virtuoso.
  • Light Linux system administration, VM setup, server specification and OS installation and updates.

Confidential, Irvine, CA

CAD Contractor

Responsibilities:

  • Bugzilla source code customization.
  • Wiki setup and support.
  • FlexLM license installation and management.
  • Specified and hand-assembled (in a 2U chassis) a high-availability/high-performance Perforce server.
  • CAD software installation and support.

Confidential, Santa Clara, CA

Senior Staff CAD Engineer

Responsibilities:

  • Extensive Perl and Skill scripting for Confidential ’s full custom layout environment.
  • Cleaned up existing, and set company-wide standards for Skill language scripts.
  • Lead the evaluation, installation and support of the Methodics VersIC design data management tool (VersIC provides similar functionality to IC Manage and ClioSoft).
  • Volunteered to be the Perforce administrator after the previous admin left on short notice.
  • Supported Virtuoso, StarRC, Voltage Storm, Installed PDK’s and FlexLM licenses. Worked with software vendors to resolve tools issues/bugs.
  • During my first year at Confidential, I was the sole CAD engineer supporting 20+ circuit designers.

Confidential, Santa Clara, CA

Senior CAD Engineer

Responsibilities:

  • Lead the evaluation of design data management software (CDSP4, ClioSoft and Synchronicity) and implementation (ClioSoft).
  • Worked with ClioSoft to add new functionality, increase performance and better align their tool with Confidential ’s needs.
  • Overhauled Confidential ’s ten year old, unwieldy (not even under revision control) mass of Skill code.
  • A two-month effort that resulted in code that was revision controlled, organized, loaded quickly and could be understood without drawing a page full of flow charts.

Confidential, San Francisco, CA

Senior CAD Engineer

Responsibilities:

  • Developed Perl, Perl/TK, Python, C, Skill and shell scripts to: Automate DRC, LVS and antenna checks for Confidential 's libraries, massage spice decks into LVS or CDL format, make spice deck IP customer deliverables hard to reverse engineer by removing all hierarchy and renumbering all nodes and devices sequentially.
  • Developed a C program to delete, copy and modify objects directly (without translation to text) in GDS files.
  • Developed a Perl script for cell and pin name consistency checks across Verilog, GDS, LEF, LVS and LIB files. Virtually eliminated cell and pin naming errors before IP was delivered to clients.
  • Physical design (placement, routing, clock tree synthesis and power grid generation) using SOC Encounter and verification (DRC and LVS using Calibre) for SPI 4.2 and PCI Express macros and test chips.
  • Developed Verilog test benches for Confidential 's SPI 4.2 macro and developed a Perl/Tk GUI based, test vector generator for the test bench.
  • Installed and maintained commercial software tools, Hercules and Calibre runsets, design management software (CDSP4) and FLEXLM licenses.
  • Setup and maintenance of Sun Grid Engine compute farm.

Confidential, Petaluma, CA

Design Verification Engineer

Responsibilities:

  • Test bench development using Verilog, Verilog/PLI and C.

Confidential, Sunnyvale, CA

Corporate Applications Engineer

Responsibilities:

  • I was responsible for supporting clients in the use of Confidential ’s tool.
  • Developed the router GDSII writer.
  • At Confidential I transitioned to a different role providing a buffer between the Sales force and R&D when technical issues impacted sales.

Confidential, Mountain View, CA

Senior CAD Engineer

Responsibilities:

  • Developed an interactive Perl/TK viewer for the viewing of post placement, standard cell designs output from Confidential ’s internally developed place and route tools.
  • Developed Perl and Skill scripts to verify and compare pre and post synthesis Verilog with the Virtuoso layout database.

Confidential, San Jose, CA

Application Engineer

Responsibilities:

  • On-site support and code development at Intel for the integration of Mentor’s place and route tools into Intel’s physical design flow.
  • Achieved an average 3X improvement in the router runtime.
  • On-site support and development at Hitachi Microsystems for Mentor’s data-path layout generator.

Confidential, Redondo Beach, CA

Senior Engineer

Responsibilities:

  • Full custom transis­tor-level circuit design, layout, behavioral modeling and simulation.
  • Developed a configurable layout genera­tor for a content addressable memory.
  • Designed a CMOS gate array library including development of the underlying base array and logic cells.
  • Standard cell library creation with responsibility for circuit design, behavioral models, synthesis libraries and supervision of layout personnel.

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