Hardware Engineering Intern Resume

OBJECTIVE:

Seeking for entry - level hardware engineer job in FPGA/VISL validation, design or testing area. Available after 5/29/2017

PROFESSIONAL SUMMARY:

Have experiences in RTL validation and synthesis, hands-on experiences with embedded system design, FPGA implementation and VISL system design. Have strong skills in VISL power dissipation analysis, VHDL coding, integrated circuit design and optimization. Familiar with programming languages like C/C++, JAVA and hardware programming language like G, Verilog. Have basic knowledges of network protocol. Personal quality: self-motivated, creative thinker, detail-oriented.

ORDER BY PROFICIENCY:

Programming Languages: Java, C, Verilog HDL, • Software Eclipse, Cadence Virtuoso, labVIEW, labVIEW C ++ , Matlab Synopsys Confidential, Modelsim PE, AutoCAD,

Platform: Linux, Unix, Windows Ma tlab

WORK HISTORY:

Hardware Engineering Intern

Confidential

Responsibilities:

Developed and implemented video single processing module in KVM and provided continued maintenance of video encoding algorithm.

Software Engineering Intern

Confidential, Chicago, Illinois

Responsibilities:

Accomplished trouble-shooting work for mobile game, responsible for establishing database of voice recognition and researched applying deep learning methods into game operating instructions.
Designed 32-bit adders and Comparator with Arithmetic Logic Unit (ALU), simulated those circuit by Confidential and analyze their path delay.
Analyzed communication protocol and mastered CRC calibration principle and calculation method, designed front panel and block diagram program for power control system.
Implemented VHDL for three dynamic branch predictors and using Modesim PE to generate the results and waves, compare the data and realize their trade-offs between power consumption and performance.
Using three register-transfer level technologies to optimize power consumption on carry ripple adder architecture in 32-bit CPU design. Implemented test-branch and RTL-code by verilog coding, completed validation and get results.

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