Analog Mixed Signal Design Engineer Resume Austin Tx - Hire IT People

SUMMARY

Experienced Ambitious Analog/RF IC Designer looking for more challenges with 5 years of working experience; Hands on Experience on circuit designing, simulations, Layout floor planning, Signal Integrity, Tape Outs, Lab measurements(Silicon testing),Smith Charts,NF,OIP3,IIP3,HD2,HD3 etc.

TECHNICAL SKILLS

Design Tools: Cadence (Spice/ HpsiceD, Virtuoso/Caliber(DRC/LVS), Spectre),Xilinx ISE 12.1

Lab Instruments: DMM,Digital OscilloScope,Analog/Rf Function generators,Clock Genrators,Temperature Controllers,Spectrum Analyzers

Programming Languages: C, C++,Perl, Verilog /Verilog A, MATLAB, Ocean Scripts

Operating Systems: Linux/Unix, MS - DOS, MAC OS, Windows (XP, 7, Vista).

PROFESSIONAL EXPERIENCE

Analog Mixed Signal Design Engineer

Confidential, Austin Tx

Responsibilities:

Low Dropout Regulator 1.2V, 22nm CMOS Si
Fixed Input voltage .6, LDO output 1V with output variation of less then 1.5%.
Phase Locked Loop 1V, 22nm CMOS Si
I'm helping the designer who is owning the PLL in doing some simulations and testing it in the lab and the analysis for charge pump /LC tank.
It's a LC Pll with fixed frequency range 4.8Ghz and consuming 5mA of current.
PLL has Switch capacitor based Iref generation for Chargepump and VCO.
Lab Measurements and Simulations
Hands on Experience on taking the measurements and simulations for LDO,BG, PLL .
Performed the task of automating the various Instruments for Measurements.

MTS Analog Design Engineer

Confidential, Sunnyvale CA

Responsibilities:

TX—capacitive feedback topology with fixed slew rate over all PVT and load variation from 10pF to 100pF for SPMI and open drain topology for I2C with VOL less then 20% of VDD for load variation from 10pF to 550pF
RX - Schmitt trigger with glitch filter for glitches of 50ns and 10ns on the clock for I2C and switching threshold of .7*VDD to VDD and 0.1*VDD to .4*VDD with hysteresis of .3*VDD.

Analog IC Design Engineer

Confidential, Irvine CA

Responsibilities:

Responsible for whole chip; Baseband Signal 3dB BW up to 10MHz for base stations applications.
Differential BICMOS Op-Amp consists of class AB output.
Gain can be varied from 0dB to 40dB as minimum and maximum gain respectively with gain steps of .5dB .
Chip had very challenging specs like High OIP3, IP3, High Swing I/p and O/p common Mode, Low power and Low Noise.
Performed HB Simulations for OIP3, IIP3; other simulations were performed for output NOISE, NF, STB, AC. ETC.
Executed the floor planning for all the sub-blocks to the top level .Post layout simulations were performed and analyzed the problems of Electro migration, IR drop, parasitic analysis etc.
Modified the circuit tricks to maintain good supply rejection even at high frequencies -20dB till 10MHz and -60dB at Dc
Circuit was simulated for Noise, Load regulation, Line regulation supply rejection, PM and transients for various cases.
Executed the floor planning of all the sub-block to the top level.