Analog Designer Resume

SUMMARY

I am a Senior Layout Engineer with a Master Degree and expertise of 7 years, proven on various ASIC designs among which the world’s best audio Digital to Analog Converter. I have a wide range experience in Analog and Mixed signal Layout design including DRC, LVS, DFM and Antenna Checks, through many Technologies & Processes to complete projects on time and within budget. I also provided RC extractions and application support for physical design.

PROFESSIONAL EXPERIENCE

Analog Designer

Confidential

Responsibilities:

Performed Layout design of many different Standard cells including DRC/LVS/DFM and Abutment checks for many Technologies TSMC 45GS, TSMC32G, TSMC28HP and GF28G.
Contributed in different projects by Performing Layout design of many Analog IPs like PLL, DLL, Comparators, Pads, and Power IPs including DRC/LVS for Technologies like TSMC45GS, TSMC28HP and GF28G.
Changed Layout of some IPs from TSMC32G to TSMC28HP for some test chips.
Implemented some new IP architecture to be used in many chips.

Senior Layout Engineer

Confidential

Responsibilities:

Performed Layout design including DRC/LVS, Antenna Checks also RC extractions and post - layout simulations of different sub-blocks of RF Micro-Tuner Project implemented with CMOS 0.15um GSMC process.
Completed Layout design of 11Bits 110MHz pipelined ADC with CMOS 90nm TSMC process including DRC/LVS/DFM and Antenna Checks.
Contributed in the Blu-Ray red laser Project by Layout design and Verifications of Digital Frequency Generator with CMOS 90nm TSMC process.
Performed Layout design, Verifications and RC extractions of 1.2V Band-gap Voltage Reference with CMOS 0.15um TSMC process used in Buck-Boost Regulator Project.
Implemented Critical changes based on post-layout simulations of RC extractions of ESS World best Audio DAC with CMOS 0.15um TSMC process.
Contributed in IBM 0.13um 2M Pixel Camera chip Project by Layout design and Verifications of Reference Voltages and Currents for different circuits.
Implemented Comparator and LDO circuits with CMOS 0.15um GSMC process used in SLIC Project.
Performed the Layout design and Verifications DRC/LVS/DFM, Antenna Checks and RC extractions of Various Analog IPs.