- A Lead Hardware Design Engineer role where my creative problem solving capabilities, technical experience, electronic, hardware and programming knowledge can be use effectively to improve operations and contribute to company profits.
- Extensive experience in design, analysis, testing and debugging analogue, mixed analogue/digital signal, digital and RF circuitry backed by numerous projects completed.
- Very low noise amplifiers, high stability oscillators, frequency synthesisers (PLL and DDS), mixers, RF switchers, high linearity power amplifiers.
- Couplers, circulators, impedance transformers
- Stripline and microstrip, transmission lone, impedance matching
- Multipath and line of sight propagation, signal to noise ratio (SNR), sensitivity.
- Modulation/demodulation techniques: FHSS, DSSS, FSK, PSK, OFDM, MSK, QAM, AM, SSB, FM, PM, TDMA, QPSK, QAM
- Wireless protocols: 802.11x, 802.16x, CDMA, W - CDMA, GPS, GSM, Bluetooth, Zigbee, Wimax, LTE, 5G, IOT
- Satellite communication: ARGUS, GOES, GPS
- RFID tags used for wildlife monitoring and container tracking.
- ADS, HFSS, Sonnet, ADS Genesys, PSpice, Microwave Office, MMICAD, Cadence Allegro, Cadence ORCAD - schematic and layout, Protel DXP
- Strong expertise in digital design and testing
- Microprocessors: PowerPC, Confidential, ARM, Tensilica RISC
- Microcontrollers: Atmel, TI, PIC, Freescale, Hitachi
- CPLD, FPGA design test and debug
- Serial interfaces and communication protocols: RS232, RS485, I2C, SPI, SMB, USB, DS3, T1, Ethernet: 10T, 100T, 1000T, 10GE, 100GE, 40GE, IEEE802.3bj, IEEE802.3bs PCI Express, M.2, mSATA.
- Parallel interfaces and communication protocols: PCI, PICx, IDE, GPIB (IEEE488), EPP, IEEE1284.
- Optical communication: OC-3, OC-12, OC-96, OC192, Fiber Channel
- Efficient in designing using basic digital components: gates, flip-flops, registers, multiplexers, latches, counters in different types of logic - ECL, PECL, SSTL, LVPECL, LVDS, CML, TTL, CMOS.
- Good knowledge of VHDL and Verilog used for PLD/FPGA design and debugging
- Good knowledge of assembly, C++, Perl, python.
- Strong expertise in High Speed Digital Design and Signal Integrity
- Design, simulation and characterisation for: PCIX, PCI, PCI Express, Fiber Channel, SAS, SATA, XAUI, DDR, LVDS, GPIO, DDR, DDR2, DDR3, DDR4, SDRAM, flash, USB, SPI, Ethernet 10T, 100T 1000T, Infiniband;
- IBIS model creation for single and differential ended I/O’s
- BER, jitter, eye diagram, crosstalk characterisation, clock distribution
- Model correlation and timing analysis
- S-parameters for line and circuit modelling and signal integrity simulation
- Characterisation of transmission lines, terminations, vias, connectors and discontinuities
- Cadence SI (SpectraQuest), Cadence SPB, HFSS, HSPICE, Hyperlynx, Timing designer, Cadence Virtuoso, XTK, PADS, ADS, Quantum SI, Sigrity
- TDR, Network Analyser Oscilloscopes, Logical analysers, Spectrum analysers.
- Strong expertise in analogue design and testing:
- Very low noise amplifiers, oscillators, active and passive filters, peak detectors, PLL, power amplifiers class A, B, AB, C, D, E and F.
- Switch mode and linear power supplies, hot-swap circuitry, redundant power supplies.
- Power management for battery power devices.
- PSpice, PCAD, ORCAD, Alegro, Eagle, Protel, PADS, LabView, MathLab, MathCAD.
- Engineering documentation: design requirements, design specification, verification plan and verification report
- Storage/black box for aerospace industry
- Signal integrity for PCI Express gen2 and 3, SAS/SATA2
- SSD M.2 SATA and M2 NVMe; mSATA; SAS and SATA drives
- Interfacing with server board, DDR3 memories, FLASH, I2C and SPI interfaces
- Power supplies and power sequencing, Clock distribution and synchronization
- SI link budget and stack-up recommendation
- Robot arm central control unit
- Design based on Confidential Atom Z8350 Cherry Trail
- Designed with: DDR3L, HDMI, USB host and OTG, MIPI, eMMC;
- Power supplies and distribution, start-up and shut down sequencing
- Battery charging circuitry for different battery chemistry
- Wireless powered sensor network for security/ surveillance application
- Various sensor networks (CO2, forced entrance, video surveillance, temperature, …) connected with a central processing unit
- Designed the central unit using an ARM processor,
- Designed the various sensors using microcontrollers for very low power consumption
- Defined the communication protocol and worked with the software team to implement it
- Research in wireless powering the sensors form various distances and location
- Designed the Tx and Rx for 13.5xMHz
- Warning system for sudden breaking or stop on auto vehicles
- Microcontroller based system with I2C busses for communication
- Bluetooth programming interface
- High power LED
Tools: used: Cadence, LTspice
Principal High Speed Design Engineer
- Research and simulations in 112Gbps
- Signal modulation for 112Gbps and beyond, FEC requirements, channel requirements
- Lead passive channel specification and collaborate with interconnect vendors (TE, Molex, Amphenol) to deliver product meeting HW design specification for 112G NRZ operation.
- Channel: PCB materials (2nd and 3rd order effects, roughness, glass weave), PCB manufacturing process, cable, and connectors
- Driving chip vendors (HiSilicon) to deliver state-of-the-art SerDes architecture through signaling technology and equalizer to guarantee NRZ 112G-SR, NRZ 56G-MR, and PAM-4 56G-LR operation with good BER with and without FEC.
- Massive MIMO system design
- Worked with suppliers: internal and external to define and research the options in designing Massive MIMO systems for 5G
- Worked with thermal and mechanical teams to establish the best tradeoff between electrical, thermal and mechanical design to meet the client requirements
- Worked with university teams in Europe to define and manage research projects for achieving best solution in algorithms; materials and components
- Mentored and supervised a team of board engineers
- High power 5G Massive MIMO
- Lead passive channel specification and collaborate with interconnect vendors (TE, Molex, FCI, Amphenol) to deliver product meeting HW design specification for 56G operation.
- Driving interconnect vendors (Amphenol, Tyco, TE, Molex, FCI) and PCB manufacturing vendors (Amphenol, Sanmina, WUs, TTM, Toppan, ISU, Multek-Germany), material vendors (Isola, Panasonic, ITEQ) to deliver high data rate channels with reasonable cost.
- Investigated the possibility to have 100Gbps on one differential pair on a low-cost PCB
- Investigate different possible modulation schemes and error correction schemes for improving the performance of the system
- Defined the layout guidelines, PCB stack-up, component placement, component selection for this project
- Worked with the CPRI standardization team on defining CPRI 7.0
- Investigated the possibility to transmit CPRI over Ethernet
- Simulations for different data rates and PCB configuration
- Worked with ASIC team to define next generation ASIC
- System architecture and design for digital interfaces CPRI, JESD204B, DDR3
- Power delivery system design for a PCB the have peak power of 6kW and mean power of 0.4kW.
Tools: used: HFSS, Cadence SPB suite. Mentor Graphics, Microwave Office, ADS.
Staff Electronics Design Engineer
- Proof of concept for 802.3bj long cables, check the maximum passive lengths
- Simulations for different dielectrics, gauge, drain wire/s
- Simulation for different metals and different plating
- Aim to build a passive zQSFP or QSFP28 over 7m
- Wireless or Ultrasound device to detect the presence of a person and if there are any issues.
- Based on a WiFi module/ultrasound device and on Doppler frequency changes in an enclosed space when an event occurs
- Proof of concept
- Design of wireless, ultrasound and digital modules
- Worked with customers to devise the best device for their needs
- Worked closely with manufacturing company to define the testing procedures for manufacturing and the optimization/elimination of yield
- Worked with mechanical contractor to design the enclosure as per client specification.
Tools: used: Cadence ORCAD and Allegro.
Lead Electronics Design Engineer
- Pre and post layout signal integrity:
- Pre-layout simulations using HFSS and ADS to generate SI rules for XAUI, PCIe gen1,2, and 3, SATA, Infiniband.
- SI guidelines generation for system and boards
- Maximum/minimum trace length
- Maximum numbers of vias, back drilling layers, routing layers
- Link budget and specifications
- Stack-up generation
- Post layout system simulation and verification
- Backplane design for 28Gbps and aiming for
- Leading edge modeling and signal integrity for next generation design - 28 Gbps
- Worked with connector and ASIC manufacturers in defining and design of products for 28 Gbps backplanes and cards.
- New ideas for PCB manufacturing to eliminate losses at high data rates
- Worked together with PCB manufacturers to define new technologies and new materials
- Simulated and defined new pads and anti-pads for high speed signals in order to minimize losses and reduce cross-talk
- Software tools used: Cadence SPB 16.x suite for design, ADS, HFSS, HSPICE, Quantum-SI, SI800, CST Studio.
Hardware tools used: High Speed scope, TDR, logic analyzer, oscilloscope, traffic generator, VNA, DMM
Staff Electronics Design Engineer/Project Leader
- Hub and remote backstation 2.3-2.8GHz and 3.3 - 3.9GHz frequency bands:
- Proof of concept
- Digital and RF architectural design
- Multi-processor design: 5 ARMS, 4 Tensilica and a NIOS
- Very low noise very high efficiency linear and switching power supplies, very low noise very low power losses linear supplies,
- Onboard communication using GMII interfaces
- Synchronization using 1588v2, SyncE and GPS
- Design for very low clock jitter, this include low noise power supplies, stack-up and routing management, low noise clock distribution system
- High speed digital design
- High linearity RF power amplifiers
- Designed MIMO RX and TX chains
- System design for achieving 256QAM 7/8; 1024 9/10.
- Compared with other competitors designs, tested the ideas and the functionality of different modules proposed improved designs or better options
- Designed for manufacturability and testing
- Selection of service providers and supply chain
- Hardware and software laboratory setup
- Interfaced with manufacturing for ICT design and improving the soldering process
- Interfaces with possible clients to get the product requirements
Software tools used: Cadence SPB 16.x suite for design and signal integrity, Altera Quartus, ADS.
Senior Signal Integrity Engineer/Senior Hardware Design Engineer
- Taught electronics engineers how to design power supplies and the best approach for PCB design
- Responsible for multiple projects for servers/storage industry
- Designed 1U, 2U and 3U backplanes for server and appliance industry
- Designed appliances and RAID configured storage starting from Confidential server boards
- Designed SAS - SATA JBOD expanders for 12 and 16 drives including serial communications interfaces, switching power supplies and microcontroller circuitry
- Wrote engineering specification and test specifications
- Performed SI testing and verification of these designs
- Lab characterization and verification of: PCIX buses, DDR memory, fiber channel, SAS and SATA drivers;
- Simulations for stack up, trace lengths, EMI, impedance matching and timing analysis using Allegro PCB SI, Hyperlynx, HSPICE and HFSS for: PCIX, PCI Express, DDR, SAS and SATA signaling and fiber channel.
- Interfaced with clients to adapt the designs for their specific needs
- Designed for test and manufacturing
- Wrote routing guidelines for the PCB designer
- Worked with internal and external clients during the design phases to implement and adapt the designs for their specific needs
Signal Integrity Engineer
- Characterized, tested and debugged multiple Confidential microprocessors for mobile industry: Hermone, Verde, Barracuda
- Created IBIS models for SATA and fiber channel I/O buffers using Analog Artist for simulations and IBIS Center for generating the model
- Signal Integrity - crosstalk, timing, EMI/EMC, transmission lines, discontinuities, power planes - for PCIX, PCI, DDR, USB, GPIO, LVDS using SpecctraQuest and Design Expert
- Generated models boards, via’s, packaging.
- Done correlation between IBIS model and HSPICE simulation.
- Signal integrity for SDRAM, microprocessors and optical RAM used in wireless industry.
- Performed simulations, worst case simulation with or without noise using e-designer and XTK, model fit of the results
- Lab verification for signal integrity
Senior Electronics Design Engineer
- Trained engineers for best practice when design power supplies
- Designed acoustic to RF converter, stability +/- 0.5ppm frequency band 142 - 174 MHz, using DDS techniques
- Wrote firmware for ATMega microcontroller using a finite states machine.
- Wrote the program for the user interface
- Designer BPF 9th order for 142-174MHz and HPF for 50kHz
- Designed matching circuitry for interface between DDS and RF side and between RF side and antenna
- Designed RS232 to UART interface for 1.8 V
- Designed ISP programmer for 1.8V microcontroller
- Designed switching power supply from 11-16V to 1.8V, +/- 5V and +/-9V
- Designed communication modules for Argos Satellite, this implies a very low power consumption PLL, stability 0.2 ppb, variable phase modulator, Manchester encoding, very sharp bandwidth - 2kHz/ channel, very good stability over a wide range of temperatures, precise RTC.
- Designed frequency synthesizer’s - RF, analogue and digital as well as the firmware and front-end programming, stability less than 0.5 ppm, in 140MHz - 402MHZ band, based on DDS synthesis.
- Designed SEPIC switching power supplies for battery powered devices.
- Designed very low signal amplifiers for hydrophones, sensitivity 130dBm, noise level 9.5nV/Sqr(Hz), active BP, LP, HP filters in the 76-220 kHz frequency range.
- Designed low noise, high amplification, and low power consumption amplifiers for 148-152 MHz. Class C, E and F.
- Designed microstrip and coaxial dipole antenna for modem communications in 430-470 MHz band.
- Interfaced with clients to adapt the designs for their specific needs
- Worked with clients for develop new designs as per client specifications
- Designed the PCB for all the projects
- Project management for all of these designs.
Senior Hardware Design Engineer
- Designed testing board for 0.5 - 3.2 Gbps Gandalf High Speed ASIC, with flexible interface (backplane, cables or optical modules), hot plug protection, monolithic PLL design, variable cable, trace length with selectable pre-emphasis
- Designed 2.5 Gbps optical transceiver module that was incorporated in DX 320 switch, responsible for electronics design, testing and simulation
- Tested, analyzed and improved for a noise-free (by improving the initial design) power delivery system of DX-140 switch; this involved process characterization/optimization, failure analysis, probe and test optimization, jitter analysis, noise analysis, testing for time and frequency domain, characterization of S-parameters and phase over frequency, eye diagram analysis
- Developed a new way for High Speed Digital power plane layout and decoupling using different types of capacitors which resulted in huge sales for Confidential
- Designed new testing procedures for Optera Connect DX according with ISO9001 and Confidential internal specifications
- PLL design for signal clock generator (SCG), delay lines for clock setup time
- In system testing and characterization for Optera Connect DX (this includes: bench testing, daisy chain shelf test with different patterns)
- Perform design verification tests to validate design requirements
- Cost reduction on DX140 switch
- Designed 150W (from 32-78 Vdc to 1.8, 3.3, ±5, ±12 Vdc) power supply for DX140, DX260, DX320, this include the inrush circuitry, voltage feedback and monitoring
- Power and analog circuitry for 4:1 combiner (four OC-48 to one OC192)
- Designed laser driver circuitry to maintain constant laser output power over full temperature range, design peak detectors, analog and digital laser bias circuitry
- Optimized PCB layout for RF performance with respect of the bandwidth of the digital signal, optimized the frequency response, minimum emissions for EMC/EMI compliance standards.
- Documentation for Design Specifications and Verification Report, ECR’s