OBJECTIVE

• Seeking a position involving system software embedded realtime firmware design incorporating driver development using OOA and OOD techniques involving
• NAND Flash diagnostics design, verification, and test at the hardware/software driver integration level.

TECHNICAL SKILLS

LANGUAGES: ANSI C/C++, Forth/Fcode, Perl, Python(3.4)/XML/Tk(8.6), Win 7, Linux/UNIX, Uboot, LILO, VxWorks(v6.1), pSOS HARDWARE SYSTEMS SPARC, cPCI, ARM9x/XScaleARM 926(SoC), Intel X86, PowerPC, ASIC(SoC), FPGA s, Flash

TOOLS: SunVTS, OBP, POST, X - Windows/Motif, Logic Analyzers, UMIX(GUI Builder), Lex/Yacc, Clear, SPARCWorks, I2ICE/iPAT(Intel incircuit emulator), Rational Rose, Eclipse(MARS), GDB, Traffic Generators/Fault-Injection, GitHub

STANDARDS: TCP/IP, UDP/IP, i2c/IPMI, IEEE-802.11-b/g WIFI, IEEE-1275 OBP, Broadcom, Marvell Open Source, TFTP, IPTV, DVB, MPEG

PROFESSIONAL EXPERIENCE

Confidential, Milpitas, California

Developer/Firmware Validation Engineer

Responsibilities:

• Developed automated tests, test plans and test procedures for SATA and NVMe/PCIe SSD Front End, Flash File System (F2FS), and Wear Leveling for firmware validation automated test.
• Including releases including Production and Validation packages(automated test suite builds targeted at firmware release types) for mass integration packages including failure analysis of my test cases and coordination of developers in the package launch and failure analysis process including bug tracking (JIRA).
• Concentrated on single to multilevel Flash (NAND) filesystem compaction, block compaction/garbage collection, physical block to logial block (FTL) mapping, block error count, wear leveling (P/E), error injection. namespace and identity management and file system formatting, Precondition pre-testcase (setup) scripts were also developed for device and testscase setup (pattern writes and fault injection).
• UART console validation utilities were also developed. Windows 7 workstations. Scripting was in Python and system coding was in C/C++, XML, with Git/GitHub, Eclipse & GDB tools (also Wing IDE). Early firmware (Linux 2.6.x on ARM CORTEX) proto releases would require DStream ARM JTAG/Debugger sometimes when switching between different customer release configurations.
• Front end firmware would sometimes to be modified. Firmware validation packages were developed as JIRA bug fixes and Fault Anaysis resolutions were packaged on a bi-weekly basis.

Confidential, Sunnyvale, California

Developer/Software/Firmware Validation Engineer

Responsibilities:

• Developed automated tests, test plans and test procedures for enterprise network storage platforms. Including releases of ONTAP 8.X/WAFL in clustermode. Concentrated in the areas of BIOS/Loader firmware, SSD Flash (NAND) cache performance accelerators, System Manager V3.0 (configuration tool GUI) to support system monitoring and filer configuration including clustering and HA topologies, developed test for SLDIAG diagnostic suite.
• Validation included Bad Block Management, Scrubbing, Wear Leveling, and Single and Multibit Fault Injection. FRU failure of flash (flash devices disabled) during stress testing using IXIA network saturation along with CPU saturation.
• Supported storage I/O interfaces FoC, SATA, and SAS on top of PCIe in HA, mirrored failover in clustered topology. Member of Root Cause Failure Analysis tiger team. Development was on Linux (4.8.x) and Windows 7 workstations.
• Scripting was in Perl & Python and system coding was in C/C++/pThread (CUnit instrumentation used) with Eclipse & GDB tools. The OS was embedded in compact Flash as dual images (upgrade/downgrade) with an additional configuration image.
• Wrote Test Desciption Specification of 90 test cases, performed 52 tests and ported drafts to ALM (AGILE) test plan and test lab modules (XML/XSLT). in 9 weeks. Also generated problem reports for any failed test cases. Techniques included FIJI (fault injection) to trigger NAND and NOR SSD failures Confirmed diagnostic suite functionality across multiple ONTAP (network storage OS) versions.

Confidential, Berkeley, California

Developer/Software Diagnostic Engineer Contractor

Responsibilities:

• Contracted implement network and system diagnostics for BIOS level testing and driver modification of systems including memory, power supplies, and network. Linux with 2.6.X kernel for driving USB and some network connection with GDB/KDB. Also used Widows XP Pro with Visual Studio. Implemented network based upon Cisco 827-4V router with IRB and TCP/IP using IOS. Developed traps in Java & C++/C to control access (including CUnit instrumentation) and prevent external source spoofing and access to unused TCP and UDP ports. Also worked with Sequioa Equities on diagnosing problems involving CPU throughput, memory loading, and network connectivity.

Confidential, Mountain View, California

Developer/Firmware Diagnostic Engineer Contractor

Responsibilities:

• Designed using OOA/OOD and integrated automated manufacturing diagnostics framework with a emphasis on module reuse for initial production run. The data storage “Data Asylum” was a multi-disk incremental backup storage with intelligence to handle multiple size SATA hardrives with basic hotswap.
• The boot loader system and diagnostics ran on Uboot (v1.1) and VxWorks Kernel v(6.1) on a Xscale ARM 926 cell in a Marvell SATA (SOC) controller. Developed boot loader timing and device initialization for embedded I2C controller/master and NVRAM CPLD. Developed SDRAM, NVRAM, Flash, I2C, PCIe/SATA/RAID (register, dma, & pio) embedded test with logging.

Confidential, Fremont, California

Software Test/Software Diagnostic Engineer Contractor

Responsibilities:

• Developed unit and system tests for expanded forward error correction Codec of digital video for IPTV, DVB, MPEG and DOD markets using UDP/IP broadcast over ethernet. Developed functional, nominal and negative tests for release of RaptorDF v10.0 for encoder and decoder.
• Tested expanded symbol conversion and resolution from schedule to block to repair for release. Worked with software architect to develop coverage matrix of new features. Development was done using Windows XP sp2 with CYGWIN and Linux / Fedora Core 5 in ANSI C/C++. Test documentation was written using Doxygen for source code.

Confidential, Sunnyvale, California

Developer/Software Diagnostic Engineer Contractor

Responsibilities:

• Designed using OOA/OOD and integrated diagnostics framework with a emphasis on module reuse for design verification lab. The framework allowed multiple Spectrum Analyzers, IqView, power supplies, arbitrary and vector wave generators, RF switches, and RF attenuators to support IEEE 802.11a/b/g based baseband and radio chipsets for Hardware Development Kit applications (ie - cell, gateway, access point, and network interface).
• I was able to detect faults in early version of 3rd party RF switch Ethernet communication using proto test program and TCP/IP protocol analyzer (sniffer). Coordinated with 3rd party to correct problem ending up with a 4 day turnaround (thanks to Fed/Ex express) involving packaging shipping new firmware update and return.
• The updated firmware was retested and worked straight out of the box. Devices needed to be integrated to use multithreaded multiple I/O ports including Serial, GPIB, and Ethernet on Windows XP platform. Ported PHY characterization testing from Borland 5 to Borland 6.
• Worked on development of Marker Edge Band testing for channed 1 and 11 or 14 (ETSI) side lob power attenuation and cross over into restricted band from with a step size goal of 44dBm. Used VISA, and SCPI based interfaces to facilitate reuse with low tool rewrite.
• The design was developed using Rational Rose UML and Borland C++ Builder 6 in ANSI C/C++.

Confidential, Santa Cruz, California

Developer/Software Diagnostic Engineer Contractor

Responsibilities:

• Designed using OOA/OOD and integrated diagnostics framework with a emphasis on module reuse for design verification lab. The framework allowed multiple multi-meters, I/O boxes, relay cards, programmable power supplies, and audio wave tools to RF(900 MHz), digital (USB), and bluetooth (IEEE 802.15) telephone headsets.
• Devices needed to be integrated to use multithreaded multiple I/O ports including RS232, USB, and Ethernet on Windows XP platform. All devices needed to have ability to log events to a common logging object/file with precision time stamps and interface to scripting languages Python and Perl as Client/Server using named pipes.
• Developed a common language interpreter which was a subset of SCPI using Lex/Flex and Yacc ported from Linux Red Hat v9.0 to Windows XP.
• The design was developed using Rational Rose UML and Microsoft Visual Studio .Net ANSI C/C++. Generated FrameMaker documentation in the form of a software detailed design specification (SDDS) with appended user guide. Project delivery schedule was generated using Microsoft Project and Excel under a very tight timeline. .

Confidential, San Jose, California

Developer/Software Diagnostic Engineer Contractor

Responsibilities:

• Designed using OOA/OOD and integrated diagnostics software for Automated Test Equipment Logic Tester Test Head Interface, FPGA and PCB. Fault isolation and functional tests were written in Java to isolate s-a-0, s-a-1, and cross talk faults in registers and memory components to include flash memory.
• Functional test were performed on FPGA’s and internal functional cells. System path tests was performed on 1.4 Ghz high speed serial path between workstation (Windows 2000) and test head along with testing of 38 bit 200Mhz test head bus with multiple pin electronics (PCB’s). Functional and connectivity testing was also performed on serial health bus (I2C) for ADC & DAC, slave components.
• Worked on standardizing diagnostic implementation methods framework in Java & C++ and documentation. Diagnostics interface programming was done using XML while test execution scripting was written in Python.

Confidential, Menlo Park, California

Technical Lead/Developer/Software Diagnostic Engineer Contractor

Responsibilities:

• Contracted to Engineering to design diagnostic software and firmware for cPCI Telco Server which supports full hot swap and cPCI. I lead a team to cover the entire system from concept through revenue release production of first and second generations of the server.
• This included design of POST firmware (Open Boot Prom) test suite to support hardware boot loading bringup and low level failure analysis. Also automated Solaris test framework SunVTS tests written in ANSI C/C++ drivers using Kstat’s and IOCTL’s to support production.
• The field replaceable units covered single board computers (VxWorks/MC860 and Solaris/SPARC), fans, power supplies, event controller, I2C/IPMI bus, cPCI bus, serial communication, and NIC’s (loopback & ping).
• Firmware test suite was used to test hardware & drivers while Solaris / UNIX software and hardware were being developed (concurrent engineering). Also test plans, test coverage matrices, and test strategy documentation and presentations were generated. Initial designs were done using Rational Rose OOA/OOD. Received SUN Network Systems Excellence for Exemplary Contribution Q3 FY 00.

Confidential, San Jose, California

Diagnostic Software Engineer Contractor

Responsibilities:

• Contracted to Engineering to design diagnostics for Automated Pattern Generation board enhancement to Delta STE Logic Tester in support of System On A Chip testing. Wrote software detailed design document using UML methodology using Rational Rose OOA/OOD along with FrameMaker 5.0.
• The functional diagnostic test framework was generated from the Rational Rose model and state diagrams in C++. The methods were written in C++ supported by Clear Case version/release control. Also handled resolution of system software SPR’s supported by DDTS.
• Also used Register Data Base Unit to generate board interface from database query file to support multi platform hierarchical development

Confidential, San Jose, California

Software I/O Engineer Contractor

Responsibilities:

• Contracted to Engineering to formulate solution to I/O test diagnostics problem (high tester return rate from field). Implemented software process of requirements, design using OOA/OOD, and test procedure specification along with specification and code reviews.
• Developed firmware diagnostics for mother board which included Ethernet, RS 232, MC68340 embedded controller, and Flash. The motherboard communicated independent I/O boards ATAPI, SCSI, IDE, Fiber Channel, and SSA.
• Used Software Development Systems C/C++ cross compiler with (BDM: Background Debug Mode) along with 68XXX assembler.

Confidential, Cupertino, California

Software Diagnostic Engineer Contractor

Responsibilities:

• Contracted through US. Caden to work in Diagnostics and Support Tools software design and modification of memory diagnostics for MPE environment. Diagnostic memory test patterns were written to function on multiple PCX-U PA RISC 8000 processors using Offline Diagnostic Environment (OS) in ANSI C.
• The following patterns were used walking 1’s & 0’s, refresh, read hammer write, write hammer read, full address, marching 1’s & 0’s, pseudo random, and binary tree tests. Faults covered were stuck at 1, stuck at 0, address cross talk, memory space accessibility, and bus mapping.
• Also generated performance bench marks and test plans.

Confidential, Fremont, California

Staff Software Engineer

Responsibilities:

• Designed and integrated diagnostics software for Automated Test Equipment Logic Tester SC212 and Wolf VXI interface, including requirements and detailed design using OOA/OOD techniques for back plane bring up tools, low/mid level(s) access primitives to registers, memory, and relays to include PLI to Verilog HDL models primarily the FPGA models. Developed logic tester SCAN calibration tool Xmotif GUI interface and timing generator access routines.
• Developed option slot configuration tool, which read hardware configurations of tester optional boards to verify test Project Folders and allow customers to use Project Folders on multiple testers without rewrite. Converted factory handler/prober interface for GPIB and STTL.