- A top - performing Product/Validation Engineer credited with many years of increasing responsibilities combining silicon characterization, WS/FT test program development, and structural testing, high speed IO testing (PCIE Gen2) and validation, DFx SCAN testing, JTAG IEE 1149 specs, test pattern conversion expertise to deliver substantial growth in highly competitive business markets.
- Strong expertise in hands-on experience with ATE testers, bench characterization tools, such as oscilloscope, logic analyzers, spectrum analyzer, and strong analog circuit theory coped with design experience in PCB design, Orcad, Allegro PCB layout.
- Highly accomplished in coding experience with Python, Perl, C/C++, Shell Script under Unix/Linux environments and Windows-based environment with excellent verbal/written communications skills in both English and Chinese.
AREAS OF EXPERTISE
- Strong Analytical Skills
- High-Level Communications
- Strategic Planning/Analysis
- High Speed IO testing
- Window System bring up
- Problem Solving Ability
- Package TP development
- Python Script Development
- Test Plan Development
- Window System Integration
- Test Case execution/Debug
- Statistical Analysis
- Post Silicon Electrical Validation
- Memory Device Characterization
- Test Pattern Conversion
Confidential, Hillsboro, OR
Window Software Integration and Debug Engineer
- Window integration, validation and debug to find out the root-cause of failures using Windebug
- Write, automate and execute integration/validation test cases on windows stack(bkc)
- Expertise on window OS, BIOS, Intel drivers, apps, third party components
- Used LTB box to debug power failures, expert in python scripting.
- Expertise on audio domain software debug, integration and test case execution
Confidential, Folsom, CA
- Supported SH2 BI testing for Intel chipset LPT-H/L thus ensured completion of qualification.
- Developed and maintained/Debugged all Burn-In related hardware/software.
- Conducted various products testing and experimental testing.
- Automated BI pattern conversion processes.
- Created and debugged sequence and test files in pre-silicon RTL validation on Full chip model for chipset.
- Conducted post-silicon BI debug, SPT-L/H BI board bias and helped with BI board design.
Confidential, Folsom, CA
Electrical Validation Engineer
- Accomplished in helping with Intel’s multiple chipset component bench testing
- Conducted post silicon electrical validation (EV) using Intel’s ITPII (In-Target Probe).
- Developed python scripts under DAL(ITPII) and Intel Python SV environment for TAP DFx registers access and automated testing/data collection with PyVISA, NI-VISA GPIB for remote measurement control.
Confidential, Santa Clara, CA
- Accomplished in establishing characterization capabilities on memory tester for Intel’s external memory group.
- Developed testing best-known-method (BKM) on memory device specification validation.
- Defined requirements, parameters and guidelines as well as stakeholder deliverables for the characterization of DRAM spec parameter changes in response to different MCP line items.
- Helped vendor in ramping up production that meets or exceeds Intel’s yield target of <200PPM.
- Drove and closed various FACRs.
- Development and validation of all kinds of test programs; supporting design engineers in developing application specific test modules for engineering data collection, prototype characterization and silicon debugging; helped with production ramp up, releasing and transferring of production TP to manufacturing sites,
- Conducted failing Pareto/rejects analysis; pattern conversion, including design.
- Developed various Perl programs for pattern conversion, pre/post silicon pattern validation and debugging.