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Systems Applications And Staff Validation Engineer Resume

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SUMMARY

  • Experienced in computer architecture/ PC board design, electronic testing, & PM, with proven skills in:
  • System design, debugging, & validation for various pcie/ sas/ sata/ usb/ nvme/ display port/ hdmi/ mipi systems, boards, or chips.
  • Managing project schedule and task details by utilizing project management tools such as reports, tracking charts, checklist and project scheduling software.
  • Author of numerous technical documents/ papers/ International Magazines & Conference Papers.
  • Coordinate the scheduling, budgeting, and material planning for OEM/ODM engineering/ manufacturing programs.
  • Designed (concept to volume deployment, very hands - on & tools development, test procedure) PanelLink (SiliconImage) Transmitter & Receiver boards set, with enhance EMC/ RFI/ ESD immunity (both Z0 & amplitude are adjustable, to lower noise reflections) (Patented Graphics/Audio/Video Encoding Algorithm, TMDS, to reduce edge transitions by 60%), of my board design works the first time (no jumpers) Thermal, 4-Corner testing, Environmental Testing. Additional features are low jitter (< 600ps Sigma measurement) (Biconnical/ Dipole/ Antenna RFI tests) phase noise, low power (with deep sleep, & transition minimization circuitry), skew tolerant transmission (feedforward during horizontal blanking) to prevent pixel corruption, 4-corner setup, Fibre Channel, & Fiber Optics ready (from Finisar) (& Motorola 100K ECL) (400 meters Optical Fiber cable to display panel, with DC-balanced design). PC is just 1.5 meter
  • RF testing & improving geometry/material of Plastic Waveguide, EM Wave Absorbers and reflect Metal for functional and measuring SI of RF products with embedded transducer (parabolic dish antenna). Return - Insertion Loss measurement / calculation for PCB / Flex. Impedance, Crosstalk, EYE and Loss targets estimation.
  • Embedded of this PanelLink LVDS technology to interface with MPEG-2 / Multimedia 3D \ Flat Panels / picture quality / Camera / color science/shift/balance / Optical / Medical Imaging Processing / Imaging sensor / MCU Design. My PCB design replaced the previous board with improvements such as, cost / test time reduction (<50%), and EMI shielding (HVS) / susceptibility. Yield improved from 30% (before my design) to 85% (my new design). Help verification/ characterization for products release. Performed reliability engineering & exhaustive-Anechoic chamber (Acoustic/ Data Acquisition) with temperature/ humidity/ vibration/ shock/ Load and HALT (Highly Accelerated Life/Stress Testing with customers) tests.

PROFESSIONAL EXPERIENCE

Confidential

Systems Applications and Staff Validation Engineer

Responsibilities:

  • Accomplished, results oriented Applications Lead, ensure the successful integration of Confidential & WW customers product lines. Starting with the pre/ post silicon release (Spec, & Notes), presentation/ design/ fab/ test/ release, to manufacturing, support & RMA analysis for OEM, & ODM product lines.
  • Design & develop high speed 9 (PCIe, SATA, USB, & DP interface HBA) Evbs with OrCAD Schematic Capture EDA/ Concept HDL (with .DSN), SI / PI (Signal/ Power Integrity) Layout and Cadence/ Allegro s/w (with .brd), for BGA/LGA/CSP packages, footprint/ pad, vias to create Faraday shield, to perform ASIC/ SSD/ HDD/ eMMC validation (scripts testing). My designs still widely used by customers (6 years so far). Corresponding ASICs shipped 1 M chips per quarter (since 2011).
  • Resolved chips/ semiconductors output stability/ reliability budgeting/ growth modeling issues and improved the product line efficiency by 40% faster. Establishing customer testing strategy/ plan (Prototype, Motherboard & Server) to reduce error rates. Managed overseas product design.
  • Debugging PCIe/ SATA/ SAS/ RAIDn/ SerDes/ DDR3 timing model in traces analyzer (lane skew, signal integrity, intermittent issues, x1 to x16 width, error traffic summary, color/ colour accuracy/ coding, triggering, STLC, defect/ bug tracking) (AHCI, IDE, NVMe, & SerDes), between Physical, Data, and Network Links, of OSI model, with Teledyne LeCroy Summit trace analyzer-10 Gbps (GT/s) (DLLP, TLP) (network protocol view, transaction view, OOB, L1, L2, (.pex) & SerialTek BusXpert trace analyzer (.ccsas), and PCIe CV 146 / 1485 Compliance/ Standard tests. Also with Spirent protocol, Mobile MIPI, NBASE-T, M-PHY, D-PHY, Ethernet-Mac (6 Gbps) lab tests (mod proprietary scripts). Work with ASIC group to detect & root cause analysis in the bug reports (JMP tool, os, bios & device driver fw) for released products & speed up the production line by 100%.
  • Failure analysis of RMA (Return Merchant Authorization/ complaints): coordinate Validation (EVT/ DVT/ PVT), ATE, PLL Jitter/ regression-scatter/ Benchmark/ Wi-Fi tests, max EYE (PAM4) diagram, RF or FPGA device/ iso-9001 environment, MM camera mechanics, GPU/CPU, WLAN, & QA/FA teams, as a team lead to monitor customer feedbacks to drive for answers for key milestones/ PCBA manufacture process/ issues (for PC, Enterprise applications & wearable platforms with Forum s/w support). Result (as a Program Manager): re-open product lines, near zero chip-rejection and regain customers confidence for 4 key projects.

Confidential

Program Manager and Technical Marketing Engineer

Responsibilities:

  • Supervising customers support, qualifying fab vender for Dynacom telecom/ Wi-Fi equipment
  • Performing Program Management and Tech Marketing for RMA technical issues.
  • Sales/Marketing with key customers, new products, detailed Spec, pricing, and bilateral NDA.

Confidential

OEM Systems Engineering

Responsibilities:

  • Manage systems design with SDK Licensees, based on the latest Confidential Embedded UltraSPARC-IIe (Solaris) based microprocessor; Compete for Reference Design Wins (with Sun’s 6 sigma failure analysis test); Systems support: with (L2, DDR2, udma 7, DRAM, ECC, SDRAM, SCSI, Router/ Switch, RAIDn drives, TCAM/CAM, RS-232 & 422, IEEE-802.xx, STB, I2C, JTAG, GPIO, UART, VRM, i86 (x86) ckt, InfiniBand, IPMI sensor/ monitoring with networking, SoC chips, Server with PXE, IBIS, VxWorks, SMT process/ fine pitch devices) from concept, design (with FPGA layout/ packages, SAN/NAS storage) to production. Received Customer-Success Award.
  • Wireless LAN, PCI Adapter (to 100 m indoor) and Building-to-Building Bridge (bandwidth reaches 4 x T1 link, & distance up to 15 miles); ZigBee wireless network, PHY chips (XAUI), mobile phone, ATM interface (cell traffic up to 2.5 Gbps) with Switch Fabric (APC640)).
  • Establish licensing support platform with Birdsnest/ Grover/ GPS systems. Plan, monitor, design review, signal integrity, Cross Talk, Ground Bounce, Hibernation, RF Interface & manufacture of the Design Kit (Tier 1, Tier 2) wearable designs program & life cycle management..
  • Key customers support strategic products in China / Shanghai/ Shenzhen.
  • Author of numerous ANs, TNs, & FAQs.

TECHNICAL SKILLS:

Networking fundamental: WAN protocols class ISDN, frame relay, & SMDS; T1, T3, SONET, WDM, satellite and microwave architecture; ABR streaming; Circuit vs. Packet switching; tunneling encapsulation. Pre-emphasis & Equalization for lossy serial link for ISI rejection (SerDes), Smith Chart, Support lab safety, procumbent, inventory and maintenance; IT Infrastructure, Gage R&R stat. HyperLynx DRC debugging environment

Language: Good negotiator, aggressive yet polite; C, & Verilog HDL (Behavioral Modeling), Linux classes; SAS Graphic/Biz/Statistics Modeling, Cadence PSPICE/ HSPICE/ SPICE/ StarSim modeling (Avant ), HFSS-Ansoft simulation, bios/ firmware/ device drivers/ scripts, Assembly, MicroProgramming (Firmware), Agile Prog Mgmt, CAD, CAM, PowerPoint, Mechanical Drawing and FrameMaker. AMBA AHB & AXI tutorial.

Tools: Unix, Scopus (Interactive Hotline Systems), MS Project, CIS, XTK analyze, Altium Designerautomation package, Motive/ Blast timing, ISIS PreVUE, (ViewLogic class), LabView automation-DUT, MEMS technology, FMEA Failure Modes Effect Analysis, DVI, Network Searching Processing, MPEG II, MPEG VII (Indexing Schemes), WaveCrest DTS JitterAnalyzer, bathtub curve (jitter PDF), TDR/ OTDR, TD Transmission, Enterprise WLAN, WPAN, margin test, 64-bit HP/ Agilent Logic Analyzers, hi-speed Oscilloscopes (Tetronix/MSO/DSO), Hyper/ Tera Terminal, BERT jitter, VNA, VDV cable tester, Power Loop/ Sequencer/ Circuit; BOM, BKM, mini SAS Expander, SFP+ Optical; pattern generators and error detectors; Keysight HP VEE .Virtualization basics, DDTS database, Phy-layer validation; SPI Flash, MHL connections, Cpk Distribution, or udma-n / prbs-n mode tests. HDI vias, PCB stack-up dimensions, routing, microstrip or strip line, & FR4 glass lamination, system DFM / DFA / DFT Evaluation, constraints for PCB design rules/ requirements, & forward and backward annotation. HEC (Compliance) for USB2.

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