SUMMARY

• Over Twenty years of experience in the Electronic, Computer Hardware and IT industry.
• Over Six years of experience in complex PCBA bring up testing, debugging, EVT and DVT.
• Over Seven years of experience in Digital industry, involved in design, development, implementation and maintenance of FPGA Design using EDA languages and tools for Digital Designs of ICs.
• Testimonies obtained for the contributions and achievements made at client places

TECHNICAL SKILLS

Processors: AMD Opteron Socket F - Dual, Quad Cores, Intel Xeon

Chipsets: HT2100/1000 HT-PCIe bridge, i41210 PCIe-PCIX bridge, 8/4/2 Gb Fiber Switches, 10/100 Ethernet

Protocols, Buses: HyperTransport, QDR, DDR2/3, Rambus, PCIe, PCIX, Local Bus, 10/8/4/2 FC, 10/100ETH, SPI4, RS485, RS232, I2C, SM, Infini Band

PCB tools: Orcad 9, Cadence16

Languages: VHDL, VERILOG, Linux, Unix, limited Shell/Perl script

Simulators Tools: Xilinx ISE 8.1i,Altera MaxPlusII, QuartusII, Model Sim EEPlus5.5a/5.2/7, Hyperlinx

Synthesis Tools: Synopsys, Synplify, Synplify Pro, ISE XST

FSM, Schematic: Xilinx ISE 8.1i,ORCAD

Timing simulation: Xilinx ISE 8.1i, Altera MaxPlusII, QuartusII, Mod Sim EEPlus5.5a/5.2. Quartus 2, Forte

Implementation Tools: Xilinx Flow Engine GUI (Translate, Map, Place and Route/Fitting (CPLD) Constraint Editor, Template Manager, NGD Build ISP JTAG programmer, Floor Planner, EPIC viewer

Methodology: Gate Level, Data Flow Level, Behavioral Level, RTL Level

PROFESSIONAL EXPERIENCE

Confidential, Mountain view, CA

Sr. Hardware Test Engineer

Responsibilities:

• Understanding and testing the AMD quad core based motherboard System/Interface architecture for DDR3 memory interfaces
• Bring-up of PCBA, Motherboard, and BIOS/hardware testing.
• DDR3 characterization, testing and validation.
• Run Design automation tests on large sample size of greater than 100 units and collect logs as part of Environmental/Thermal analysis
• Debugging and isolation of issues and bugs before and while running the tests
• Summarizing and publishing results for review

Confidential, San Jose, CA.

Sr. Hardware Test Engineer

Responsibilities:

• Understanding and testing the NAS/SAN based storage System/Interface architecture comprising of Xeon, Opteron Processors, HT2100, HT1000, i41210 and Super IO chip sets.
• RAID5 and RAID 10 based Disk control systems.
• Hyper Transport, 10/8/4/2Gb Fiber Channel, Network Interface(ETH), DDR2 characterization, PCIe, PCIX, PCI, Local Bus, LPC and I2C protocol testing and validation.
• Done CPLD, FPGA, and PLA testing. Validation of PSU, fans and battery charging circuitries.
• Bring-up of PCBA, Motherboard, and BIOS/hardware testing in large data storage, NAS/SAN systems.
• Use of shell scripts to automate the test for validation.
• Various signal integrity characterization, tests, analysis and validation for EDVT, DVT.
• Performing EMI/EMC tests on unit modules and on whole systems.

Confidential, San Diego, CA

Sr. Systems Hardware Design Engineer

Responsibilities:

• Modules designed and worked are FCC, EUV and BWCM which are all using 10mbps serial communications.
• Understanding the System/Interface architecture specifically control signal functions for different types of Laser Systems.
• Done wide range of industry standard high speed serial protocols like SPI3/4.
• Various Bus protocols like Local Bus, Serial communications like I2C, UART supported by Host interface. This lead to the understanding of various chips architecture like PLX9030 and SRAM.
• Knowledge of differential signal control interfaces.
• Verification of Fire Control FPGA, Serial interface FPGAs, Bandwidth Control FPGAs, extended UV laser control interface with RAM architecture using Spartan3 series FPGAs.
• Done system level architecture, integration, testing and software evaluation support.
• Wide use of Logic analyzers and test equipments.
• Production failure analysis and root cause findings.
• Validation, documentation before release of design and product.
• Multiple design, production team interaction.

Confidential, Hillsboro, OR

Senior Network Engineer

Responsibilities:

• Understanding the Chip architecture specifically signal functions, PCI interfaces.
• Wide range of industry standard network PHY protocols like UTOPIA1/2/3, POSPHY2/3/4, SPI3/4, CSIX and C provided by MSF interface.
• Various Bus protocols like Local Bus, M bus and Serial communications like I2C, UART supported by XPI interface. This lead to the understanding of various chips architecture like PLX9056, Intel2114P2Pbridge and QDR/DDR SRAM.
• Knowledge of Validation platform which supports Intel SARM Microprocessor.
• Knowledge of Various Buses Functional Models.
• Verification of SysControlFPGA, XPI and MSF interfaces using various BFMs in an automated method.
• Board bring up, testing, remote support and Emulation support.
• Active participation in schematic, PCB layout design architecture and writing routing rules for PCB layouts.

Confidential

Hardware Design Engineer

Responsibilities:

• Identify the Glue Logic required for the Microprocessor interface of the switch core.
• Understanding the Chip architecture specifically signal functions from Processor interface side.
• Knowledge of Intel XSCALE processor chipsets 80310(80200up with 80312 companion)
• Motorola MPC860, Power PC architecture, IDT 79RC32355 architecture.

Confidential

Hardware Design Engineer

Responsibilities:

• Understanding the function, specifically signal functions, BModule interface, Microprocessor (SA) interfaces, IBSwitch core and PCI interfaces.
• IB Architecture Rev1.0-Vol 1 and 2
• Various Serial communications Bus protocols like System Management Bus, I2C bus, ICMB and BMspecific BML protocol.
• This lead to the understanding of various chips’ architectures like Intel Switch core, IntelSA110 Processor, Intel 21285companion chip, and DRAM.
• Other peripheral components/modules like MAC, PVxB, PHYs, SERDES, and Power Supply cage.
• Glue FPGA design includes writing structural VHDL modules for I2C, Smbus, Nine BMLs, SDFPGA, RESET logic, ICMB and Xbus I/O read and write for internal registers.
• Each modules were successfully Synthesized using Synopsys (and Simulation using ALDEC wave form viewer). Integrated top module was synthesized using Synplify. Simulation was done after synthesis using ModelSim. (.Vhm)
• Synthesized design was implemented in XC2S200-5FG256 after constraints had been edited. Implemented design was again simulated with the TOPMODULE TESTBENCH to verify timing violations/functional behavior. (.Timesim.sdf)
• Participated in many Design Review meetings, which brought in a lot of valuable design knowledge.

Confidential

Software Consultant

Responsibilities:

• Study of Parent design from Confidential . This module consists of CPLD EPM7256SQC208, TMS320C6XP, and 33/40MHZ SWITCHABLE CLOCK OSCILLATORS, ADDRESS BUFFERS 74ALB16244,DATA TRANSEIVERS74LVTH16 2245,SBSRAM MT58LC64K32D8, SDRAM TC59S1616AFT, AUDIO CODEC CS4231A and other peripheral devices.
• In the above EVM CPLD of ALTERA was designed using ABEL HDL. The top level Hierarchical module uses 1.Reset Control 2.User Control 3.Clock Selection 4.Memory Decoding 5.Interrupt Control 6.PCI Interface. PCI interface was designed with larger State Machine.
• Developed totally an indigenous EVM board keeping maximum devices unchanged other than CPLD XC95108-7-PC84, SBSRAM MT58LC128L32PT5, SDRAM MT48LC4M16A2T, PCI 2040 and clock of 20 MHz
• CPLD interfaces with PCI as GP-HOST signals and with DSP as EA signals with common 8-BIT DATA bus and separate 6-BIT ADDRESS bus. CPLD decodes addresses and controls signals. Reset, Power down and Interrupt logics are included.
• Behavioral modeling using VHDL. Constraints edited for GCLK, Pin locking and synthesized.
• Implementation is carried out and necessary modifications were done to fit the design into available physical component.
• Net list created was exported into EXEMPLAR LOGIC and synthesized for comparison of OPTIMISATION between tools.
• MACROCELLS used were 57/108, Pins used were 66/69.
• Finally design was downloaded into the device. Device performance was tested and found up to the requirement.

Confidential

Software Consultant

Responsibilities:

• Involved in the development of system card profile according to field requirement.
• Bug fixing of cards with digital simulation through PCAT and Simulation panel exclusively designed for this. Testing of system in pair in communication mode or stand alone with looping.
• Installation of system in duplicate at site over a stretch of 60Km in a suburban section having 7 stations installed with 18GHz MW tower. Installation of the system includes Busiest route of high-speed train traffic. Maintenance of systems as per Contract Agreement with Railways.
• Participated in discussions with high level Technocrats/officers for inputs and feedbacks.
• Downloading of .bin files to EPROM programmer and fusion of EPROM 27256(32KB).