We provide IT Staff Augmentation Services!

Individual Contributor Resume

3.00 Rating

SUMMARY:

  • 10+ Years of Experience:
  • ASIC and Confidential verification
  • Post tape out validation
  • Constraint random verification
  • Creating reusable verification architecture using System Verilog & UVM
  • Block level & System on Chip (SoC) verification
  • Hands on experience with formal verification
  • Team Lead & Mentoring

PROFESSIONAL SKILLS:

HDL Language: VHDL, Verilog

HVL: System Verilog

Methodology: UVM

Programming Language: C, C++, Assembly

Protocol: AXI, Bluetooth, Avalon

Domain knowledge: FFT/IFFT, Company specific protocols

Scripting: Shell, Perl, Python

EDA Tools: NCSim, Simvision, Xilinx ISE, Modelsim, ePlanner, vManager, IEV

Operating System: Linux, Windows

EXPERIENCE DETAILS:

Confidential

Individual Contributor

Skills/Tools: System Verilog, UVM, NCSim, Simvision, Eplanner

Responsibilities:

  • Creating Universal Verification Component
  • Integrating Confidential in a top level environment
  • Creating block level tests
  • Creating Reference Model
  • Assertion and Functional coverage coding
  • Verification Closure

Confidential

Individual Contributor

Skills/Tools: System Verilog Assertions, NCSim, Simvision, IEV

Responsibilities:

  • Power supply and ground connection to each cell
  • Switch (company specific analog switch) verification
  • 27 input XOR logic verification
  • Assertion based approach was used to verify all connectivity. To verify power supply connections (OR more generally point to point connections) all we needed was straight forward assertion. But to verify connectivity through switch, we needed some modifications in behavior model of chip. Unwanted logic was black boxed during the verification.

Confidential

Verification Lead

Skills/Tools: System Verilog, UVM, C++, NCSim, Simvision, ePlanner

Responsibilities:

  • Created verification plan using ePlanner tool. Generated .doc file and send it to designer for the review. Implemented review comments. This was ongoing activity while other testbench components are getting developed.
  • Created all required interfaces and integrated in the testbench. As there were multiple blocks, testbench was created using defines ( ifdef) to isolate updates for each block.
  • Created a system verilog component to mimic AXI switch matrix functionality. This was done as actual piece of RTL was going to be available in later time frame. Integrated this component in the testbench.
  • Created reusable transaction classes. As this was pipelined architecture, same transaction class was used between the blocks. This eventually added more fields to the transaction class. do compare method was implemented to compare only required fields in the transaction class.
  • Created Interface Universal Verification Components (IUVCs). When required this IUVCs just had a monitor to sample transaction on the interface and send actual transaction to scoreboard. All expect transactions to scoreboard were coming from Reference Model (RM). These models were created in C++ and I have no role to play in that. Though, while debugging failure I used to debug those RMs and report issues.
  • Created reusable sequence library and API classes. This structure was so useful that all sequences just have to call APIs. Layered sequence approach was taken.
  • Written functional coverage and assertions
  • Mapped all elements (TC, CHK, COV) to verification plan
  • Analyzed functional coverage and code coverage.
  • Created directed test sequences to fill coverage holes.
  • Running simulation tests by providing IP address of host computer was connected. With a port forwarding set, traffic get diverted to the MEP (module embedded processor). MEP eventually sends PCIe transaction to the chip
  • Python access. Provided python routines to read and write register, I had created many test routines to directly run using python
  • MEP binary program. This is a c++ program, compiled using cross compiler such that binaries can be executed on MEP. This was to avoid latencies through socket.

Confidential

Verification Lead

Skills/Tools: System Verilog, UVM, C++, NCSim, Simvision, C (firmware), ePlanner

Responsibilities:

  • Creating verification plan and getting it reviewed by designer. Implemented review comments and bringing verification plan to closure.
  • Extended existing driver component of and IUVC and override it to achieve specific functionality
  • Single testbench was created and isolated with defines to support verification for all 3 Confidential
  • Layered sequencing architecture was created to support common configuration across different Confidential .
  • Coded assertions and functional coverage.
  • Mapped all elements (TC, CHK, COV) to verification plan
  • Analyzed functional coverage and code coverage. Created directed test sequences to fill coverage holes.

Confidential

Senior Verification Engineer

Skills/Tools: System Verilog, UVM, C++, NCSim, Simvision, vManager

Responsibilities:

  • Creating verification plan and getting sign - off from designer
  • Created test sequences to verify pattern generator.
  • Creating pattern compare IUVC and verify independently as master/slave connection. This Confidential samples signal which are at known offsets from each other. Transaction class needed to have a do compare method to compare transaction when a particular field is set.
  • Created required interfaces and integrated IUVC in testbench
  • Coded assertions and functional coverage.
  • Analyzed functional coverage and code coverage. Created directed test sequences to fill coverage holes.

Confidential

Verification Engineer

Skills/Tools: System Verilog, NCSim, Simvision

Responsibilities:

  • Modifications to the environment and reference model
  • Running regressions

Confidential

Verification Engineer

Skills/Tools: VHDL, C, NCSim, Simvision

Responsibilities:

  • Updating environment according to the change in RTL
  • Update existing test to work for this environment
  • Running Regressions.

Confidential

Verification Engineer

Skills/Tools: VHDL, C, NCSim, Simvision

Responsibilities:

  • Running existing test of I2C, SPI, GPIO and JTAG
  • Running regressions

We'd love your feedback!