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Electronic Controls Engineer Resume

5.00 Rating

Cedar Rapids, IA

SUMMARY:

DSP Electrical/Electronic Controls Engineer seeking employmentfor distributed control systems, MATLAB Simulink modeling, Kalman Filter design, ladder logic PLC programming, VHDL Confidential design,or embedded firmware design for real - time operating system.

KEYWORDS:

Matlab, Simulink, Rtw, Poses, Neural Network, Hybrid, Petri-Net, Vme, Siemens, Plc, Simatic, S7, Wincc Hmi, Kalman Filter, Dsp, Aldec, Active-Hdl, Modelsim, Vhdl,Verilog, Orcad, Pspice, Pads, Blazerouter, Xilinx, Vivado, Actel, Libero, Confidential, Psos, Vxworks,Fuzzy Logic, Simulation,Dvm, Oscilloscope, Logic Analyzer, Spectrum Analyzer, Vector Analyzer, Hp Advisor, Protocol Analyzer, Ethernet, Tcp/Ip, Udp/Ip, Perl, Xcel, Cvs, Svn, Unix, Linux, C, Pascal, Forth,Fortran, Texas Instruments, Analog Devices, Cypress, Serial, Hilt, And Passport

AREAS OF SKILLS, ABILITIES, AND EXPERTISE INCLUDE:

PROGRAMMING LANGUAGES: C, PASCAL, FORTH, PETRI-NET, FORTRAN, Liberty Basic (Visual Basic)

SUMMARY OF EXPERIENCE:

Confidential, Cedar Rapids, IA

Electronic Controls Engineer

Responsibilities:

  • Utilized Synplify Pro, Questa Sim, Questa Verify, Quartus II, and Matlab Simulink Co-simulation to analyze and trouble-shoot latest designs on Confidential ArriaV, CycloneV, and Stratix Confidential ’S.
  • Linux work environment used to run modified scripts for Clocks/CDC to check for Clock Domain Boundary Crossing issues as part of Questa Verify.

Confidential, Prescott, AZ

Codec Engineer

Responsibilities:

  • Responsible for VHDL designs utilizing the Xilinx Artix Confidential, which interfaced to a TI Codec through SPI and I2S interfaces.
  • Used AXI4 Memory Mapped, AXI4 Streaming, and AXI4 Lite network topology for both interfaces.
  • Xilinx Vivado, ModelSim, and ALDEC Active-HDL ALINT were tools used to complete the design.
  • Developed several Finite State Machines with SEU mitigation as part of the SPI interface.
  • Created Verilog Bus Functional Models for test bench simulation runs of a Software Definable Radio (SDR) design.
  • Contract was for a short duration and not perm.

Confidential, East Aurora, NY

Controls Engineer

Responsibilities:

  • Developed VHDL code for a hydraulic control actuator system.
  • Design operated at 32MHz utilizing Actel RTAX Confidential with triple redundancy.
  • Created MATLAB/SIMULINK model and used “COSIM” capability to test Confidential design.
  • Components designed included a “timestamp” for MIL1553 bus messages, PWM excitation outputs for Linear Voltage Differential Transducers (LVDT’s), “STATE CONTROLLER” sequencer which mitigated SEU’s, and an ADC controller followed by demodulation to obtain positional data from the LVDT’s.
  • Utilized Actel Libero Designer for PAR and Synplify Pro for synthesis.
  • Performed “timed” simulations with SDF files utilizing ModelSim. Mentored CO-OP’s in every facet of the design process.
  • Hardware designs were completed and contract was terminated.

Confidential, Clearwater, FL

VHDL Consultant

Responsibilities:

  • Remote work done on transferring a 32 MHz design from a “Cool Runner” Xilinx CPLD to a Lattice CPLD.
  • Design was modified so as to work with Lattice Diamond PAR tools, utilized “Synplify Pro” for synthesis and ModelSim for “timed” simulations using post PAR Simulation Delay Files (SDF). Job was complete in under a month.

Confidential, San Diego, CA

VHDL Design Engineer

Responsibilities:

  • Design high speed VHDL code for Software Definable Radios.
  • Implemented control and status registers, SPI interface, and RF discretes for Intelligent Test Adapters.
  • Synthesized VHDL designs with Synplify Pro, placed and routed with Xilinx Vivado which targeted the Xilinx Kintex Confidential device. Simulated VHDL designs with ModelSim and Active-HDL.
  • Created complex state machines with Active-HDL (FSM Editor) which used multiple VHDL processes.
  • Utilized Enovia Synchronicity DesignSync configuration tool for all designs.
  • Utilized Xilinx SysGen DSP builder to create Core Generated VHDL code.
  • Designed DSP algorithms with MATLAB Simulink and utilized HDL Coder for auto-generating RTL code, and executed Embedded Coder (Real-Time Workshop) for creating C code of DSP algorithms.

Confidential, Endicott, NY

DSP Design Engineer

Responsibilities:

  • Developed Confidential design for ARINC429 System on a Chip which included a single transmitter and receiver.
  • Wrote test- benches for DO-254 testing requirements.
  • Enhanced existing Confidential design and VHDL test bench for GE38 jet turbine rate sensor as part of Full Authority Digital Electronic Control (FADEC).
  • All work was done with Mentor Graphics ModelSim SE, Synopsys Synplify Pro, and Actel Leonardo Spectrum.
  • Designed Diplexer for UAT ADS-B Transceiver (978 MHz) RF multiplexing with ATCRBS Transponder (1030 MHz and 1090 MHz).
  • Completed both LP and HP (Notch Filter) distributed component designs utilizing LINC2 and SONNET.
  • Contract was completed and DOD sequestration was in effect.

Confidential, Phoenix, AZ

Senior Design Engineer

Responsibilities:

  • Converted existing Xilinx Confidential schematics to VHDL and created test bench for code coverage, toggle coverage, path coverage, expression coverage, branch coverage, and profiler coverage using Active-HDL.
  • Created VHDL state machines as needed to support DO-254 requirements utilizing Active-HDL.
  • Synthesized Confidential designs with Synplify Pro (Synplicity) and place-routed with Xilinx Design Manager (XDM).
  • Job was completed ahead of schedule and may require remote location follow on work.

Confidential, Rowlett, TX

Design Engineer

Responsibilities:

  • Perform design and test bench creation for Confidential design using both VHDL and Verilog. Use SOPC builder for NIOS II soft processor design.
  • Use Confidential Quartus for specialized component placement which are not standard library parts.
  • Use Eclipse package for 'C' code test creation which runs on emulated EPCS-16 serial configuration device/component.
  • Convert StateCad state machines to Active-HDL to meet DO-254 requirement.
  • Designed 70MHz narrow-band passive BPF utilizing LINC2, Z-Plot, Linear FilterCad, and SONNET.
  • Tested actual design with Rohde Schwarz Spectrum Analyzer utilizing Tracking Generator.
  • Evaluated frequency response, phase shift, group delay, and reflection coefficients.
  • Performed Smith Chart Analysis to establish stability of design with component Scattering Parameters.
  • Created RF diplexer design ‘C’code program so that UAT may be RF multiplexed with ATCRBS/Mode-S for long antenna paths.
  • Presently designing a TI EMIF Avalon Master which interfaces to Confidential SOPC Builder for the Nios II.
  • Interfaced Hercules Cortex ARM uP (16-bit) to EMIF (32-bit) GPS Correlator.
  • Utilized 4NEC2 antenna design software to analyze Fractal design of GPS Micro-Strip slot antenna.
  • The GPS antenna’s radiation pattern, directivity, gain, polarization, and the impedance bandwidth was computed and displayed in 3-D for FAA .
  • Researched DO-229 GEO Bias Analysis tool data file input, so as to correct SBAS GEO and GPS signal parameters which are not matched.
  • Determined Gain, Phase, and group delay parameters for additive values from LNA, Receiver IF, GPS Antenna, and lossy transmission line.
  • Utilized SONNET to measure current density of GPS Antenna, find ideal 50 ohm feed location, and obtain data from Smith Chart and Bode Plot.

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