SUMMARY:

To obtain a FPGA design / Verification / Embedded Software position and utilize my skills in RTL design, bench creation, behavioral modeling, script writing, Embedded Programming, and debugging.

PROFESSIONAL EXPERIENCE:

Confidential

Consultant

Responsibilities:

• Member of the Emulation Verification / Validation team for a microcontroller based SOC.
• Created custom, embedded firmware for functional and integration testing of a SOC / embedded design.
• Based on existing test plans, created “bare metal” firmware closely related to the hardware implementation to stress corner cases of a design from a system level perspective.
• This custom embedded firmware would emulate system level functions such as reset or embedded runtime operations to stress the design at a higher system level.
• Writing Software test cases Emulating / and documenting the results, for the new platform
• Running tests on Mentor Veloce Emulators. And creating Test Cases
• Developed Hardware and Software Platform CSI 2, using a USB 3 Converter that takes a MIPI Output from a Sensor Camera and displays it on to a PC / Mac system
• Developed Code for the Embedded ARM 9 Processor inside the USB3 CSI converter.
• Configured The Toshiba Bridge for parallel to serial Output.
• Debugged USB 3 issues.
• Debugged the configuration issues to the Bridge, and the CMOS sensor, Indian issue.
• Debugged the issue with the MIPI Interface, configuration issues.
• Re - wrote the Code for the different sensors, Color, and black and white.
• Debugged the CX3 Driver issues.
• Designed and tested a Digital Display unit, that carries a Lazer Dome
• Performed a Sham test, and a Regular test on the Lazer assembly domes, for the clinical trials, with different detector assemblies. And Plotted the graphical output for both Tests on an Xl sht.
• Helped in the debug of the embedded Rani Micro Transmitter.
• Developed Apps (C.G.I.) for the Camera in windows using visual for the Environment.
• RE-configured the Development Software Bridge for 1.8/2.8 V CMOS Color camera operation.
• Re wrote the USB Driver descriptor file.
• Debugged Raw 10, 12, and YUV format issues, picture quality and tuning.
• Debugged using Bus Hound.
• Brought up a total of 22 MIPI Based cameras.

Confidential

Firmware Engineer

Responsibilities:

• Updated camera Sensing circuitry (stereo type) with LED output for synchronization to the exposure.
• Tested the Charging circuitry for the Led section using IR.
• Updated the Schematics accordingly.
• Modified / Debugged the charging circuitry for the LED section to provide more current for the LED’s
• Tested different camera platforms. Generate IQ comparison report.

Confidential

FPGA Consultant

Responsibilities:

• Design/mod/porting design across different Xilinx platforms,
• Design verification, test benches. Lab bring up/debug
• Design and verification on FPGAs including the Kintex7 on Ultrasound systems
• Debugging of an existing code for design issues using Vivado.
• Converting the PCIe speed from 2.5 to 5.0 G (Gen2 to Gen 3) at 4 lanes, on PCIe link, testing for the stability of the link at that speed.
• Debug Kintex 7 design issues on image processing;
• Write scripts to automate the digital board Testing.
• Used Per force for Source control, and Jenkins for build and release the code.
• Used eXpress SW, as a data base for the different systems.
• Accelerated hands-on implementation and training of system Verilog, and UVM
• Completed a workshop for developing assertions, and created test benches for UVM Environment.
• OOP’s based FPGA verification Development contained Sequences, Agents, Config. space
• Completed Analysis ports, Scoreboards and Random constraints. Developed UVM test benches for the UART DUT. Perl scripts were used for automating the process. Also ASIC design flow
• Created Test bench arch, verification architecture, Verification flow, Functional Coverage, Code Coverage, Assertions.

Confidential

Debugging Engineer

Responsibilities:

• Tuned, trouble shot, and debugged FPGA firmware on various existing driver boards
• Debugged DSP (TMS320 series) Interface to the FPGA for booting issues.
• Debugged the FLASH memory accessing from FPGA and DSP
• Debugged temperature detectors (Sensors) for reading an incremental Temp. changes
• Tasks were implemented using VHDL RTL.

Confidential

FPGA Emulation / Validation Engineer

Responsibilities:

• Pre-Silicon Functional Validation
• Project One - ASIC NIC Emulation, Formally Server Engines
• Planned and performed Serdes validation and characterization, the following was done on FPGA platform:
• Characterized Skyhawk ASIC at 25 - 30Gig on Confidential NIC card, using IXIA Packet gen, and Scope for Eye Template of the Output, by programming LSI GUI for different parameters to obtain optimal results.
• Carried out validation on Vertex 6 and 7 using two different Emulation Platforms, for two different FPGA’s, by sending Packets from the Scapy/Python scripts, for different Protocols.
• Conducted Serdes validation and characterization on the Proof of Concept for the Confidential Stratix 5 FPGA, using Loop Back method on the Confidential Stratix 5 development Board.
• Performed the following on the FPGA platform:
• Mapped ASIC Corsair into 6 vertex 7 FPGA’s (Gemini) Platform.
• Performed the build/synthesis/mapping of the Corsair 100 G Asics.
• NCSI Filter tests, VLAN test, Unicast test, Broadcast test
• LLDP Packet/filter tests, MGMT Pass thru tests, mailbox Test
• Conducted arbitrator test, OS2BMC Frame Filter test, systick, systimer, rr error test, NCSI Echo Packet testing, Block 10 testing UART, I2C master, MDIO Master, MDIO slave testing.
• Performed soft reset testing: configuring the SGMII to match the speed of the Marvell.
• Wrote test document for regression testing.
• Ethernet Block Test to bring-up and test an Ethernet SGMII MAC/PCS and Network Processor using an ARM Cortex-M0.
• Emphasized debugging throughout the entire project.
• Wrote validation test cases in TCL for validation setup.
• Built SoC Emulation Models with the focus on validating the DFT/Debug features.
• Converted RTL-simulation based tests to emulation test content.
• Tested Layer 2 and Layer 3 protocols using Python and Scapy scripts.
• Implemented automation framework and script development using Scapy Framework
• Implemented python coding and debugging.
• Implemented version control/defect tracking tools like GIT, bugzilla.
• Used Xilinx Vivado for Chip scope Debugging, Partial building of the project.
• Completed simulation and regression tests on the 100 Gig Asics, for different protocols FCoE and 40Gig.
• Tested different protocols implemented inside the ASIC, TCP/IP, LLDP and UDP, Netc filters, Broadcast
• Used wire shark analyzer and Packet Gen for debugging.
• Performed Tx and Rx testing of high speed serdes.
• Performed EDVT post silicon validation of high speed IC.
• Project Two, Confidential On Stratix 5 Porting the 100 Gig ASIC code into an FPGA
• Validated a 40G Ethernet MAC/PCS using an Confidential Stratix V FPGA.
• Implemented a different PCIe IP from (MTIP) for the FPGA, instead of the ASIC one.

Confidential

FPGA Engineer for System Programming

Responsibilities:

• Focused on in system programmability.
• Added serial Interface UART, I2C. clk, Brought up UART and serial Interface.
• Work completed on MSP430, using TI’s Code Composer and associated /debugger,
• Developed knowledge of basic framework setup on the MPS430F5510-SDK board:-
• Made timer code work using default 1.045MHz internal clk configurable for 100Hz or 1kHz tic timer API uses milliseconds, resolution is in ms (resolution is 10ms or 1ms, Respectively) LED blinking at 1Hz
• Performed basic HW config. header files setup for MSP430F5510-SDK and 2M.
• Setup the Framework for I2C slave and power down modes.

Confidential

FPGA Engineer

Responsibilities:

• Designed Analog Converter Board and FPGA for a Digital Spec.
• Analyzer, which provides Amplitude info.
• Processed I and Q data stream, using Small (6-10 tap) FIR for Gaussian filter, needed on both I and Q data streams, a Power detector that generates (I 2 + Q 2), this also handles case of (1 2 + Q 2) = 0. Design also contains a Log Detector for generating LOG10(I 2 + Q 2), also generating DAC Output using SCALE / OFFSET for the DAC, and a Video Amp and a 10Mhz and a 10Khz Low Pass filter stage at the Output. 4-corner testing, Also document code requirements.
• Implemented lvds pattern checker: a Code to handle pattern detector for test pattern from the Spec Analyzer.
• Used Spyglass-power,tool for power estimation of the design.

Confidential

FPGA Test Engineer

Responsibilities:

• Implemented Ethernet Testability on a vertex 5 FPGA-base S.O.C. IP for the Network Protocols: Ethernet-AVB IP core, MAC, GNET, Cobra Net, VLAN, etc.
• Implemented on a vertex 5 FPGA-base S.O.C. IP the following Network Protocols
• Ethernet-AVB IP core, MAC, GNET, Cobra Net, VLAN, etc. using the Micro blaze soft-core proc. from Xilinx as an Embedded Processor, and Linux as OS, IP creation, Peripheral, PCIe, DDR memory, configuration and control ofPHY's, and Interrupts. The above mentioned SOC was functionally verified
• Implemented the wrappers and the I/F’s for the different Peripherals, e.g. I2S etc.. and external memory (DDR2, SDRAM & Flash) using Xilinx XPS environment
• Brought up DSP (DSP21369zx,shark Fin) bds. with different configuration inputs.
• Wrote code for SPI Flash Writer for ADSP-21369 and the Atmel Flash, for boot Loader and Linux kernel Porting.
• Maintained Dash Board for different boards using VB generated GUI Interfaces, and also Python for writing Test scripts. Designed Test Fixtures for the Digital Boards. And EMC / EMI testing (4 corner testing)
• Designed, developed, tested and debugged of Atmel Ucont software, and JTAG issues.
• Wrote Diag. code for the Power supply outputs .
• Added a Loop back feature into the MAC’s for testability.
• Used the following network analyzer IPERF, and Wire shark in order to determine and analyze the performance of the UDP and TCP protocols.
• Used Altium Tool for the Confidential rules and Electrical verification.
• Back light dimming is a new modulation technology developed for varying the intensity of the LCD / LED display technology (Back Light Dimming) or the control of LED's

Confidential

FPGA Engineer

Responsibilities:

• Developed FPGA Spec (DOC) for the SOC verification purposes, for a Global Lightening Mapper
• Facilitated the collaboration of fellow employees to perform verification and synthesis for High Speed, RAD HARD, FPGA designs. The FPGA contained different I/F’s e.g. Space Wire, Manchester EN/DEC, Decoder, SPI, PCIe, SerDes.
• Maintained spreadsheet interface between the Hardware and Software for different addresses (Offset), its contents, and description.
• Used scripts to conduct Simulation /Verification, and synthesis on the Present Design RAD HARD - Motor Control, VHDL Test Benches, and Test Scripts, for a Near-Infrared Camera.

Confidential

FPGA Engineer

Responsibilities:

• Developed an Add-on Card for H.264 Encoder Product, which takes the DVB/ASI Mpeg2 Transport Stream and converts it to a G751 E3 Stream: “E3 Interface for a Trunk Card” (Add-on Card Slot to the Existing Encoder Platform. The Add-on Card is 4” X 6”)
• Bd. consisted of a Spartan 3E Xilinx, Functionally Simulated in Verilog, and a Framer/De-Framer, and a 8051 Ucont. Originally the Ucont.
• Carried out all the Config. for the Framer / De-Framer, all the Config. Functions for the ASIC was transferred to the FPGA

Confidential

FPGA Engineer

Responsibilities:

• Added different features to existing Lattice XP2 FPGA code to accommodate customer requirements, along with fixing of existing Bugs, e.g.
• Access code implementation for the D.U.T. using Lattice Reveal Soft Core Insertion module, together with their reveal Logic analyzer. (Full Logic Analyzer Support)

Confidential

Hardware Engineer

Responsibilities:

• Developed IP Network Surveillance Camera Solution, HDR Video Camera
• Facilitated and conducted the design of a custom-made Sensor Bd. using either an Aptina Sensor or a Cypress Sensor(CMOS) plus Video Processor Bd.
• Lead in the design of the video Processor Bd. using a TI DSP DM355/365, plus a Power Bd. with P.O.E. option.
• Responsible for the day-to-day operations of the Hardware development Platform for the IP-Based HDR camera, a Battery mode (Green) camera, and Wireless 802.11 (WiFi)
• Designed a Green Camera (battery-operated) Pwr. With the Solar Battery Charger being Implemented on one Of the Bd.s. which allows the Camera to operate w/o outside Pwr .
• Wrote C Programs for “N and Reader out” for an e-sys in order to read the contents of the FLASH (UBL, UBOOT, ECC, UIMAGE(Linux OS), RAMDISK, environment variables) and NAND Programming.
• Continued Testing of the P2P feature in windows Envi. And brought up over 10 IP Cameras using TI Code Composer.

Confidential

Hardware Engineer

Responsibilities:

• Designed Rev2 of an ATCA blade MTI (10GE CCA which was used as a Maintenance and Test I/F, for capturing and playback of data. Ground System Architecture.
• Interfaced with Manufacturing to complete the FTP’s/ ATP/FAT’s Test for the above Bd.
• C.T.F. Programmed/Debugged/Tested/Verified F.O.R’s (GUI, 207, MTU) in the Rack with LabView GUI.
• Data Link FPGA for Linking two Planes, distributing Time Tag Inf., and CRC. B) Mind Speed FPGA for Cross Point Switch connecting the XAUI (802.13) to Fabric. It also contained a PPC Core, and an IPMC circuitry, which was leveraged off an existing design. S.I. was performed on the MTI, using Hyper Lynx
• UDP Protocol for the Ethernet Protocol. A2) Memory Controller for the DDR 2, and Xpack Optical for the Front End, A3) Utilized PCIe Gen2 at 2.5G
• Wrote the necessary documents for testing using Lab View
• Debugged number of CSIB bds., has two UDP channels, with VxWorks running; Using Xilinx EDK Tools
• Completed a Loop Back test between two Bds.
• Troubleshot and Repaired High Bandwidth communication cards which were labeled “Beyond Repair” to save the company/program approx. $500,000.
• IRAD (FTM “Lazer Com”) Adoptive Optics- Project for implementing the IRAD (MEMS-Optical Switching-Compensating for distortion)
• Lead an effort for a proof of concept design of Lazer Optics
• Supervised the development of the Embedded system and integration task.
• Implemented the IRAD (MEMS-Optical Switching-Compensating for distortion).
• Project Specifics:
• The H/W is a VME based system to be upgraded to a PCI, made up of SBC (Aitech)
• A.D. DSP (21161) shark Fin Multiprocessor Bd. (Bittware). Porting Kit was used to port TS148 bridge, AD Fins (Bridge), Cluster Busses, AD DSP’s and local memory over to the SBC, and HyTec ADC Bd., which had 64 channels at 16 bits. The ADC Bd. was used to convert the Analog data.
• Device Driver for the HyTec ADC Bd. is recognized by the VxWorks.
• Bittware tools were used to run different diag. on the DSP’s and a bittware server for remote login into target.
• Created Modules for RTOS-VxWorks to write & read to the DSP’s and its local memories.
• Created HIL libraries that ran under VxWorks.
• Signal Processing analysis using MATLAB.
• Write DSP code for a Bittware Multi-DSP Processing Platform, in order to implement a Proprietary positioning Algorithm . “Algorithm for Closed Loop Control”.
• Wrote C Code For Controlling and Mapping the 140 Actuators inside Mirror Device Driver Box.
• Designed Custom-Made USB Device Driver (for the High Voltage MEMS Driver).
• Wrote code to Initialize and configure Aurora High Speed Core, in a Vertex II.
• Used Bittware Tetra Card for ADC Interface to the Bittware Cluster Bus, to AD Shark DSP’s.
• Designed Initialization routines in Asm. for DSP card to Initialize an Atlantis Switch to Route
• Different High Speed Signals To / From Bitware Tetra card to the Dsp’s and SerDes.

Confidential

FPGA Engineer

Responsibilities:

• Established and carried out the design for PCI / PCIX Platform
• Produced a detailed design of a PCI / PCI-X Core plus User I/F Logic for Controlling and Interfacing to different R.F. Mod., Up/Down Converters. The SPI I/F’s supplied Data, Clk, and Latch enables to different RF Interfaces
• The RF I/F’s consisted of the following: 1- Serial To Parallel Shift. Reg. 2- DDS Synth. 3- Atten. Etc. Bit Banging Method was utilized on the DDS I/F.
• Integrated the PCI/PCIX core, Also a Complete set of Tcl files were generated, and PCI Master/Target Scripts were generated to supplement the present Verification /Test Benches. The RTL for the PCI/PCIx Wrapper was done in VHDL, and the Slave “RF I/F’s” was done in Verilog. The Design was Debugged in a both Embedded and Bridge Environment. Also PM (Power Management was Implemented).
• Designed Functional block to contain an Sram I/F, and a DMA I/F. The design was a PCI compliance, and fit inside a Confidential Cyclone. BGA. The Design was Debugged in Embedded and Bridge Environment.
• Implemented design in PXI Form factor, to fit inside an PCI Instrumentation C/Cage.
• Carried out S/W checkout using N.I. S/W for Low Level Debugging, plus Labview 8.2 for the whole System.
• Designed a Frequency Counter Confidential CPLD 9xxxx Series to determine the frequency input.