OBJECTIVE:

To obtain a Software Engineer with many years of professional experience in research, analysis, design, development, implementation, testing and bug - fixing for telecommunication system, Video,Audioproducts. Optimization and integrating of variousaudioand video codec on different processors/DSP. During my career, I've developed software for image processing, digital communications systems,Audio DSP, embedded systems, statistical data analysis.

SUMMARY:

• Expertise in and Implementation of FPGA, hardware, Board Design, Scripts (TCL, Python, shell, Perl), ASIC verification, debug, Tests.
• Negotiating contract for design resources and manufacturers locally and overseas.
• Planning, executing, and overseeing of multi-discipline teams including HW Design, Board Design, Confidential development, software development, mechanical and thermal design, PCB layout/Routing.
• Product design for R&D and Manufacturing development according to client specifications
• Ensuring Product Compliance (4-corner Testing)/certification.
• Ability to organize and oversee employees in project design and development.
• Proactive and result-driven leader with extensive experience in Networking, Video (display).
• Preparing SOW and specifications for customer.
• Implementation and technical management in Sensors, Emulation, HDR Cameras, System Programming
• Strengths:
• Ample experience in hardware (Board design) / Integration / Validation.
• Proof of concept; successfully carry out projects from beginning to end.
• Successfully collaborate with employees from multiple disciplines
• Ability to provide expert direction on technical matters
• Extensive experience in producing thorough status reports and presentations
• Participated in all aspects of design reviews for a Board.

EXPERIENCE:

Confidential

Responsibilities:

• Implemented Integration of IP cores for TCP / UDP IP Off Load Engines for 10 Gig, 25 Gig, and 40 Gig.
• Full TCP/UDP offloading Customizable Silicon IP.
• Integration of the IP with the Low latency Mac.
• Integration of the IP with the Xilinx Mac, PCS/PMA.
• Also developed a low latency Mac well integrated within the IP.
• Dual 10G SFP+ ports. Jumbo frames No-Interrupt Architecture. Up to 128 Virtual NICs Multiple DMA engines for high throughput, For different platforms, Xilinx, and Confidential
• DDR Interfaces for 3, & 4, was added to the main User.IF module as a generic Interface, if needed
• Generated User manual.
• Completed Xilinx Certification for the Ultra Scale FPGA’s, suite 1,2,3
• Completed Xilinx certification for the Zynq series on Vivado HLS tool chain Using UDP / TCP IP soft cores.
• Completed Xilinx Certification for the Embedded System Hardware Design.
• Completed Xilinx Certification for the ULTra Scale Memory Transceiver and Migrating to 7S-Us V2016.3
• Presently Working on the Embedded System Software Cluster.

Confidential

Consultant

Responsibilities:

• Member of the Emulation Verification / Validation team for a microcontroller based SOC.
• Created custom, embedded firmware for functional and integration testing of a SOC / embedded design.
• Based on existing test plans, created “bare metal” firmware closely related to the hardware implementation to stress corner cases of a design from a system level perspective. This custom embedded firmware would emulate system level functions such as reset or embedded runtime operations to stress the design at a higher system level.
• Writing Software test cases Emulating / and documenting the results, for the new platform
• Running tests on Mentor Veloce Emulators. And creating Test Cases
• Proficient in designing and implementingembedded software/firmware inC/C++ and assembly.
• Designed and implemented newaudiofeatures on TI.

Confidential

Consultant

Responsibilities:

• Developed Hardware and Software Platform CSI 2, using a USB 3 Converter that takes a MIPI Output from a Sensor Camera and displays it on to a PC / Mac system
• Developed Code for the Embedded ARM 9 Processor inside the USB3 CSI converter.
• Used Keil compiler environment with JTAG/JLINK segger J-Link Ultra Hardware.
• Configured the Toshiba Bridge for parallel to serial Output.
• Debugged USB 3 issues.
• Debugged the configuration issues to the Bridge, and the CMOS sensor, Indian issue.
• Debugged the issue with the MIPI Interface, configuration issues.
• Re-wrote the Code for the different sensors, Color, and black and white.
• Debugged the CX3 Driver issues.
• Designed and tested a Digital Display unit, that carries a Lazer Dome
• Performed a Sham test, and a Regular test on the Lazer assembly domes, for the clinical trials, with different detector assemblies. And Plotted the graphical output for both Tests on an Xl sht.
• Helped in the debug of the embedded Rani Micro Transmitter.
• Developed Apps (C.G.I.) for the Camera in windows using visual for the Environment.
• RE-configured the Development Software Bridge for 1.8/2.8 V CMOS Color camera operation.
• Re wrote the USB Driver descriptor file.
• Debugged Raw 10, 12, and YUV format issues, picture quality and tuning.
• Debugged using Bus Hound.
• Implemented the above protocol inside the Confidential spartan 6 using off the shelf core.
• Brought up a total of 22 MIPI Based cameras.
• Worked on Audio DSP responsible for developing a scaling audio, Music and Sound Processor analysis exploitation tool.
• Implementation language wasCrunning on an embeddedLinuxplatform.
• Subscriptions toaudiocontent, dealt with day-to-day technical troubleshooting, managedlinux-based web servers and streamingaudioservers.
• TIDSP (Digital Signal Processor)assembler programming.

Confidential

Software Engineer

Responsibilities:

• Updated camera Sensing circuitry (stereo type) with LED output for synchronization to the exposure.
• Tested the Charging circuitry for the Led section using IR.
• Updated the Schematics accordingly.
• Modified / Debugged the charging circuitry for the LED section to provide more current for the LED’s
• Tested different camera platforms. Generate IQ comparison report.

Confidential

Consultant

Responsibilities:

• Building FPGAs from scratch, design/mod/porting design across different Xilinx platforms,
• RTL with VHDL and Verilog.
• Timing closure and optimization, STA
• Design verification, test benches.
• Lab bring up/debug
• Design and verification on FPGAs including the Kintex7 on Ultrasound systems
• Serdes data acquisition, bus interfaces.
• Signal processing blocks.
• Video processing blocks
• Music and Sound Processor (DSP)
• Video pipe, audio/video drivers
• Memory interfaces.
• Software inCfor power switcher
• Converting the PCIe speed from 2.5 to 5.0 G (Gen2 to Gen 3) at 4 lanes, on PCIe link, testing for the stability of the link at that speed.
• Debug Kintex 7 design issues on image processing,
• Write scripts to automate the digital board Testing.
• Used Perforce for Source control, and Jenkins for build and release the code
• Ioptimized there present Confidential code for there infrared camera, to fix the critical warnings, that show up during Build of the camera code. Also created an SDC (constraint) file for them.
• Accelerated hands-on implementation and training of system verilog, and UVM/OVM
• Completed a workshop for developing assertions, and created test benches for UVM Environment.
• OOP’s based Confidential verification Development contained Sequences, Agents, Config space
• Completed Analysis ports, Scoreboards and Random constraints. Developed UVM test benches for the UART DUT. Perl scripts were used for automating the process. Also ASIC design flow
• Tested bench arch, verification arch,Verification flow, Functional Coverage, Code Coverage, Assertions.
• Designed and developed Confidential firmware (VHDL) for photonic detector driver boards
• Tuned, trouble shot, and debugged Confidential firmware on various existing driver boards
• Collaborated directly with system software team in the development of total solution for products
• Conducted and participated in design and code reviews Maintaining source codes and related documentations
• Debugged DSP (TMS320 series) Interface to the Confidential for booting issues.
• Debugged the FLASH memory accessing from Confidential and DSP
• Debugged temperature detectors (Sensors) for reading an incremental Temp. changes
• Tasks were implemented using VHDL RTL.

Confidential

Emulation / Validation Engineer

Responsibilities:

• Project One - ASIC NIC Emulation, Formally Server Engines
• Planned and performed Serdes validation and characterization, the following was done on Confidential platform:
• Characterized Skyhawk ASIC at 25 - 30Gig on Confidential NIC card, using IXIA Packet gen, and Scope for Eye Template of the Output, by programming LSI GUI for different parameters to obtain optimal results.
• Carried out validation on Vertex 6 and 7 using two different Emulation Platforms, for two different FPGA’s, by sending Packets from the Scapy/Python scripts, for different Protocols.
• Conducted Serdes validation and characterization on the Proof of Concept for the Confidential Stratix 5 FPGA, using Loop Back method on the Confidential Stratix 5 development Board.
• Performed the following on the Confidential platform:
• Mapped ASIC Corsair into 6 vertex 7 FPGA’s (Gemini) Platform.
• Performed the build/synthesis/mapping of the Corsair 100 G Asics.
• NCSI Filter tests, VLAN test, Unicast test, Broadcast test
• LLDP Packet/filter tests, MGMT Pass thru tests, mailbox Test
• Conducted arbitrator test, OS2BMC Frame Filter test, systick, systimer, rr error test, NCSI Echo Packet testing, Block 10 testing UART, I2C master, MDIO Master, MDIO slave testing.
• Performed soft reset testing: configuring the SGMII to match the speed of the Marvell.
• Wrote test document for regression testing.
• Emphasized debugging throughout the entire project.
• Wrote validation test cases in TCL for validation setup.
• Built SoC Emulation Models with the focus on validating the DFT/Debug features.
• Converted RTL-simulation based tests to emulation test content.
• Tested Layer 2 and Layer 3 protocols using Python and Scapy scripts.
• Implemented automation framework and script development using Scapy Framework
• Implemented python coding and debugging.
• Implemented version control/defect tracking tools like GIT, bugzilla.
• Synopsis synthesis tool - Simplify pro in Linux was used for the FPGA’s.
• Used Xilinx Vivado for Chip scope Debugging, Partial building of the project.
• Completed simulation and regression tests on the 100 Gig Asics, for different protocols FCoE and 40Gig.
• Tested different protocols implemented inside the ASIC, TCP/IP, LLDP and UDP, Netc filters, Broadcast
• The ARM Processor had to be configured with separate C Routines for the following tests:-
• 1- Debug test, 2- MailBox, 3- Mutex Test., 4- NCSI echo test, 5- rr error test, 6- rr test, 7- systick, 8- systimer test, 9- ncsi filter test, 10- LLDP filter test, 11- Arbitration test
• Used wire analyzer and Packet Gen for debugging.
• Project Two, Confidential On Stratix 5 Porting the ASIC code into an FPGA Carried out Proof of concept and characterization for Serdes on the Startix 5
• Organized and conducted physical design, floor planning, global and local clock distribution, automatic place and route.
• Presented project results to department
• Added serial Interface UART, I2C. clk.
• Brought up UART and serial Interface.
• Work completed on MCU MSP430, using TI’s Code Composer and associated /debugger,
• Developed knowledge of basic framework setup on the MPS430F5510-SDK board:-
• Made timer code work using default 1.045MHz internal clk configurable for 100Hz or 1kHz tic timer API uses milliseconds, resolution is in ms (resolution is 10ms or 1ms, respectively) LED blinking at 1Hz
• Performed basic HW config. header file setup for MSP430F5510-SDK and 2M.
• Setup the Framework for I2C slave and power down modes.

Confidential

R&D / Test Engineer

Responsibilities:

• Implemented Ethernet Testability on a vertex 5 FPGA-base S.O.C. IP for the Network Protocols: Ethernet-AVB IP core, MAC, GNET, Cobra Net, VLAN, etc.
• Implemented on a vertex 5 FPGA-base S.O.C. IP the following Network Protocols
• Ethernet - AVB (AUDIO) IP core, MAC, GNET, Cobra Net, VLAN, etc. using the Micro blaze soft-core proc. from Xilinx as an Embedded Processor, and Linux as OS, IP creation, Peripheral PCIe, DDR memory, configuration and control ofPHY's, and Interrupts. The above mentioned SOC was functionally verified
• Implemented wrappers and the I/Fs for different Peripherals, e.g. I2S etc. and external memory (DDR2, SDRAM & Flash) using Xilinx XPS environment
• Brought up DSP (DSP21369zx,shark Fin) Bds. with different configuration inputs.
• Wrote code for SPI Flash Writer for ADSP-21369 and the Atmel Flash, for boot Loader and Linux kernel Porting, and PIC for Pwr supply measurements, and Atmel Ucont for Inf to the Analog bd.
• Maintained Dash Board for different boards using VB generated GUI Interfaces, and also Python for writing Test scripts. Designed Test Fixtures for the Digital Boards. And EMC / EMI testing (4 corner testing)
• Designed, developed, tested and debugged of Atmel Ucont software, and JTAG issues, and DDR II issues.
• Added a Loop back feature into the MAC’s for testability.
• Used the following network analyzer IPERF, and Wire shark in order to determine and analyze the performance of the UDP and TCP protocols.
• Used Altium Tool for the S.C., Electrical rules and Electrical verification.
• Validate DDR II Interface, and Interfaced to the OLED circuitry for the safe / Normal mode operation.

Board Engineer

Confidential

Responsibilities:

• Established and completed the design, using Spartan 3E FPGA, for video processing for back light dimming (Local Dimming) on a LED displaywhichcontrols the PWM mode; the PWM is the normal mode for driving the LED, in the back light dimming mode.
• Spartan 3E Confidential is a new modulation technology developed for varying the intensity of the LCD / LED display technology (Back Light Dimming) or the control of LED's.
• Developed Confidential Spec. Documentation for the SOC for verification purposes, for a Global Lightening Mapper, for the Space Wire FPGA
• Facilitated the collaboration of fellow employees to perform verification and synthesis for High Speed, RAD HARD, Confidential designs. The Confidential contained different I/F’s e.g. Space Wire, Manchester EN/DEC, Decoder, SPI, PCIe, SerDes.
• Maintained spreadsheet interface between the Hardware and Software for different addresses (Offset), its contents, and description.
• Project 2 - Near Infrared Camera Project
• Used scripts to conduct Simulation /Verification, and synthesis on the Present Design RAD HARD - Motor Control, VHDL Test Benches, and Test Scripts, for a Near-Infrared Camera.
• Communicated progress with department/management
• Developed Add-on Card for H.264 Encoder Product, which converts DVB/ASI Mpeg2 Transport Stream to a G751 E3 Stream: “E3 Interface for a Trunk Card” (Add-on Card Slot to the Existing Encoder Platform. The Add-on Card is 4” X 6”)
• Bd. consisted of a Spartan 3E Xilinx, Functionally Simulated in Verilog, and a Framer/De-Framer, and a 8051 Ucont. Originally the Ucont.
• Carried out all the Config. for the Framer / De-Framer, all the Config. Functions for the ASIC was transferred to the FPGA
• Performed the following for functional operation of Up-Down Converters
• Added different features to existing Lattice XP2 and ICE40 Confidential code to accommodate customer requirements, and fixed existing Bugs, e.g.
• Implemented access code for the D.U.T. using Lattice Reveal Soft Core Insertion module, together with their reveal Logic analyzer. (Full Logic Analyzer Support)
• Modified the Confidential, specifically the code in Confidential EP1C12FGA in Test set Integration unit to meet customer requirements.
• Assessed and fixed existing Bugs, using Quartus S/W with Signal Tap II Logic Analyzer.
• Modified the Visual basic program to accommodate new customer requirements.
• Ran Simulation Test Benches on the above Code using HPVEE for testing.
• The P.C. I/F was a combination of RS232, & I2C. The D.U.T. I/F was a S.P.I.
• Fixed bugs on board w/ Flash I/F and the D.U.T.
• All the above work was for the functional operation of the RF Up-Down Converters.

VP of Operations and Hardware Engineer

Confidential

Responsibilities:

• Developed IP Network Surveillance Camera Solution, HDR Video Camera Low Power Platform
• Strong knowledge of CMOS camera design with imaging experience
• Supervised daily operations of the Hardware Development Platform for IP-based HDR camera
• Facilitated and conducted the design of a custom-made Sensor Bd. using either an Aptina Sensor or a Cypress Sensor(CMOS) plus Video Processor Bd.
• Lead in the design of video Processor Bd. using a TI DSP DM355/365, plus a Power Bd. with P.O.E.option.
• Responsible for day-to-day operations of the Hardware development Platform for the IP-Based HDR camera, a Battery mode (Green) camera, and Wirless 802.11 (WiFi)
• Designed a Green Camera (battery-operated) Pwr. With the Solar Battery Charger being Implemented on one Of the Bd.s. which allows the Camera to operate w/o outside Pwr
• Wrote C Programs for “Nand Reader out” for an e-sys in order to read the contents of the FLASH (UBL, UBOOT, ECC, UIMAGE(Linux OS), RAMDISK, environment variables) and NAND Programming.
• Continued Testing of the P2P feature in windows Envi. And Brought up over 10 IP Cameras using TI Code Composer.
• Designed a High Speed video Image data Camera using “Virtex-5 FPGA”, which continuously looks for the synchronization codes coming on the SYNC channel from the High Speed Sensor and collects the video image data accordingly.
• Process continues until ‘n’ frames are written into onboard SDRAM (n = 35 on power on, onboard 2GB memory is available, max n = 670). These frames are written at sensor operating speed. Real time Confidential handles the raw image data from sensor and stores into memory in real time.
• The stored ‘n’ images are slowly readout as per USB bandwidth completely before capturing next set of images.
• This Confidential was also implemented for a Solar Pwr High Speed Camera (Sensor).
• Supported F.C. Core 1.2 Gbps wrapper for Vertex 4, and completed Error injection along w/ test solutions.
• Involved in Coin Cell Powered Active RFID TAG
• Designed a WiFi 802.11.5.4 Platform, with a Jennic Ucont. based Embedded system and a Flash, and USB For a Reader, and a TAG for an active RFID system.
• Designed LCD display Interface for TI DM355 for a security camera.

Hardware Engineer

Confidential

Responsibilities:

• Designed Rev2 of an ATCA blade MTI (10GE CCA which was used as a Maintenance and Test I/F, for capturing and playback of data. Ground System Architecture.
• It contained two Sections:
• Common Section had the following: A Data Link Confidential for Linking two Planes, distributing Time Tag Inf., and CRC, Power Management B) Mind Speed Confidential for Cross Point Switch connecting the XAUI (802.13) to Fabric. It also contained a PPC Core, and an IPMC circuitry, which was leveraged off an existing design. S.I. was performed on the MTI, using Hyper Lynx
• Payload section (custom section) contained the following: FPGA’s / I/F’s: A) UDP Protocol for the Ethernet Protocol B) Memory Controller for DDR 2, embedded ARM, and Xpack Optical for Front End C) PCIe at 2.5G
• FPGAs contained eTDG (test generator) and eTDM (Monitor) as a means for testing the XAUI I/F’s.
• LabView (10.x) GUI was used for Programming & Performing the testing of the FTP of the Bd. features.
• Implemented the portioning of a serial flash for the different sections.
• Communicated with manufacturing to complete the FTP’s/ ATP/FAT’s Test for the above Bd.
• C.T.F. Programmed/Debugged/Tested/Verified F.O.R’s (GUI, 207, MTU) in the Rack with LabView GUI.
• Data Link Confidential for Linking two Planes, distributing Time Tag Inf., and CRC. B) Mind Speed Confidential for Cross Point Switch connecting the XAUI (802.13) to Fabric, also contained a PPC Core, and an IPMC circuitry, which was leveraged off an existing design.
• Performed S.I. on the MTI, using Hyper Lynx.
• Validate DDR II Interface
• Supported Test and Integration of the following Bds.:
• TTU (Time Tag Unit) & FOT(Fan Out Tx) in the ATCA chassy with the MTI.
• CTF Racks, consisting for many different FOR’s; used an FOT and TTU chassy along w/ an E2O H/W and OTO S/W I/F.
• Debugged CSIB Bds., containing two UDP channels, with VxWorks running; used Xilinx EDK Tools
• Completed a Loop Back test between two Bds.
• Debugged a number of MTI Bds. which had different problems ranging from the DDR2 memory issue to the Dale/Mind Speed. Used Xilinx Chip Scope, and JTAG SCAN Tools.
• Troubleshot and repaired High Bandwidth communication cards which were labeled “Beyond Repair” to save the company/program approx. $500,000.
• IRAD (FTM “Lazer Com”) Adoptive Optics- Project for implementing the IRAD (MEMS-Optical Switching-Compensating for distortion)
• Lead an effort for a proof of concept design of Lazer Optics
• Supervised the development of the Embedded system and integration task.
• Oversaw and advised two Interns, and a software employee.
• Implemented the IRAD (MEMS-Optical Switching-Compensating for distortion).
• Project Specifics:
• Re-Designed the Blue Tooth / ZigBee Platform 802.11
• Designed a Programming Test Fixture “Structure” to be used for programming the Baby Blue Tooth Bds.
• Redesigned the Baby Blue Tooth Platform using the ST.Micro ARM7 UCont. And ST2500 Tx/Rx. to provide more flexibility for the embedded platform. For more PWR, implemented Zigbee platform with Tx/Rx Switches and an LDA on Rx Side to improve the Gain.
• Re-Designed and Re-layout the Regular Blue Tooth Board using PCB Designer Front end, and ALEGRO for Layout.
• Split software Stack to accommodate the flexibility of using different vendor chip.
• Established and carried out design for PCI / PCIX Platform
• Produced a detailed design of a PCI / PCI-X Core plus User I/F Logic for Controlling and Interfacing to different R.F. Mod., Up/Down Converters. The SPI I/F’s supplied Data, Clk, and Latch enables to different RF Interfaces“Up-Down Converters”
• RF I/Fs consisted of the following: 1- Serial To Parallel Shift. Reg. 2- DDS Synth. 3- Atten. Etc. Bit Banging Method was utilized on the DDS I/F.
• Integrated PCI/PCIX core, Also a Complete set of Tcl files were generated, and PCI Master/Target Scripts were generated to supplement the present Verification /Test Benches. The RTL for PCI/PCIx Wrapper was done in VHDL, and Slave “RF I/F’s” was done in Verilog.
• Debugged design in both Embedded and Bridge Environment; Implemented Power Management.
• Designed functional block to contain an Sram I/F, and a DMA I/F. The design was a PCI compliance, and fit inside an Confidential Cyclone. BGA. The Design was Debbugged in Embedded and Bridge Environment.
• Implemented design in PXI Form factor, to fit inside a PCI Instrumentation C/Cage.
• Carried out S/W checkout using N.I. S/W for Low Level Debugging, plus Labview 8.2 for the whole System.
• Designed Frequency Counter Confidential CPLD 9xxxx Series to determine the frequency input.
• Detail Board level design of a 32 bit MCU (MPC5200B) 2nd Gen. for an Embedded systems bd. which had the following low Pwr RF Devices: Cellular, WIFI (802.11), Bluetooth, and GPS.
• Implemented all the above I/F’s thru the serial busses, eg. I2C, SPI, USB Busses coming off the MCU. Also a CAN I/F, and J1939, J1587, J1850 for different vehicle busses.
• The Bd. also contained different DC-DC Pwr Conversions (LDO & Linear), and Pwr Management Ccts., and an Ethernet Cont. An IO expander CPLD, I2C, RTC., etc….
• Wrote Ass. Code for a PIC UCont. (Slave) for an I2C IP Core for Temp. Measurement
• Wrote Verilog code for an IO Expander for an Confidential CPLD.
• Debugged Verilog code for an Ethernet Mac Layer for MII Cont. Interface, also Debugged the whole Ethernet Tx/Rx channel with the Dual Sram Controller for the problem of Dropping Ethernet Packets.
• Wrote test benches for Ethernet section, and Commented the whole code.
• Utilized Chip Scope for the debugging.
• Interfaced with Atmel Ucont.
• Developed the DSP code for AD21161 shark Fin DSP 32bit Processor to implement the following.
• 1-Channel Linearization for A/D ASICS; 2.-Gain Tracking, (Internal & External); 3-Trim Table Read/Write, Offset Trim; 4-Input Offset Minimization; 5-Linearization Calibration; 6-Data Collection; 7-Error Correction; 8-Diagnostic data mode; 9-Implementing the Heart Information; 10-Asic Reset/Register Test. for supporting the ASIC'S; 11-Dynamic Allocation.
• Completed the above for a image processing for CT system.
• Carried out the detail design of a Local / Global backplane.
• Developed a Visual Basic Code for a Debugger/Performance Tool for the verification of a L.U.T.
• Developed a Perl Script for a Extraction/Implementation for the Translation LUT.
• Ensured product conformed to ISO 9001.
• Used Boot loader on all dsp software
• Developed an RTL code for a Graphics Controller.
• Completed RTL Code Development in VHDL, and Validation of the design for a Video Display section.
• The Functionality of the code included a Graphics / Frame Buffer Controller for a Flat Panel Display. And a Controller for a Dual Port Display Sram. I2C Bus was also implemented inside the Design for configuration purposes. Using Model Sim for Development Env.
• Integrated a Model of the IDT Dual Port Sram in the Test Bench - design was synthesized for a Vertex II Pro.
• Participated in all design reviews for the Bd.
• Debugged VOIP Platform.
• Tested and Debugged a DSP Platform for a VOIP Application, the Bd. Consisted of an MSC 8103 Core DSP and Three MSC8122 DSP’s “in order to provide the correct number of voice channels” for the TDM Processing.
• Modified the Abel Code inside the Main CPLD “Xilinx 9750” on the MPC 8280 Base Bd. To accommodate the LED Protocol Implementation for the Line Cards, The Digital E1/T1 I/O Card, and the Analog I/O Card.
• Performed Confidential Design for Timing and Measurement card
• Carried out detail design of a B LTD Bd. (Reference Timing and Measurement Card) for a synchronization system, utilizing a Vertex II Confidential for generation of reference signals e.g. 1PPS and measurement of its offset w.r.t. to other signals.
• Utilized the Generation of alarms and other Command and Control Interfaces, SPI Bus I/F, UART I/F
• It generated a 1PPS signal, which is synchronized with the other Clk signals. It is synchronized to the Main 1PPS signal under S/W control. The front end of the board was an Analog input, with an RF Attenuator and an OP. Amp’s and Converters. Also some of the RF section had R.F PWR Splitters and some more Attenuators.
• Prepared the above design using Mentor tools. “HDL Designer”, both HDL (VHDL) and graphical Capture, board stacking and trace simulation was done using Hyper Lynx Tool.
• Conducted background investigation
• Completed work for a Major Defense Contractor: Detail Design of the Mode Boards for emulating different modes, for the purpose of testing the S/W. The Mode boards were made up of 4 Xilinx “Spartan” FPGA’s, a VXI I/F, 3 CPLD’s (one for Decoding, and another one for programming the Flash with the Bit Stream). This was a second generation product with new modes and repackaged bds. The modes themselves were designed and linked
• Simulated in S.C.; Mode Bds. were debugged using Digital Scopes and Logic Analyzers.
• Designed VHDL/TB code of a VXI Bus Interface, using Cypress 37K Series CPLD’s with Warp. The code was written using VHDL.
• Designed VHDL /TB code of the M-Module Bus Interface for the DMM carrier M-Module’s, also designed the Propertery “Duart” serial O/P Interface for the DMM itself.
• Designed VHDL code for the M-Module I/F’s for the M-Modules carrier for the multiple M-Module’s on board the carrier.
• Designed VHDL /TB code for the Teck. Replacement Modules for a Programmable Digital TTL I/O for different Bytes.
• Designed optically isolated version of the above-mentioned replacement Bd.
• Designed VHDL code for controlling relays in a switching bds. and in Main VXI Bk plane.
• Designed a PCI Target (Slave) in View Logic S.C. for controlling relays in a Switching system.
• Carried out Detail Design in S.C. for a 12 Channel A/D board and 12-channel D/A board: both are Teck. Replacement boards.
• Designed USB Controller in VHDL Code to Control a Rabbit Ucontroller chip for the Transferof data from the Ucont. to VXI Backplane.
• Implemented design in a Cypress CPLD.
• Used 2D Field Solver for Signal Integrity.
• Remained responsive to Customer Interface Requirements.
• Used LabView S/W “5.x” for testing the above-mentioned Bds. / Projects.