Senior Systems Modeling Engineer Resume

SUMMARY:

6 years of experience in semiconductor domain - Confidential flash memory modeling and Confidential design/verification
Proficiency in system level modeling, block level RTL design and debug, coverage based verification and Confidential flash sequence flows.
Possess hands on knowledge of industry standard tools such as NCsim, Virtuoso (LVS/DRC), Spectre, Visual studio.

RELEVANT SKILLS:

C, C++, UNIX operating system, Verilog, System Verilog and Perl Working knowledge of ARM protocols such as AMBA (AHB + APB), AXI

WORK EXPERIENCE:

Senior Systems Modeling Engineer

Confidential

Responsibilities:

Responsible for implementation of multiple features of software models belonging to current and upcoming generations of Confidential flash memory, which are then utilized by firmware teams for validation and optimization purposes.
Assist and occasionally mentor firmware teams across the US and India, in debug and testbench design efforts
Personally devised a UI in Linux which enables even first time users to successfully test commands on encrypted Verilog designs of various memory types belonging to the sub 19nm family (1bit/cell, 2bits/cell and 3bits/cell)
Detected and reported bugs in the model and sequence flow using this setup. The resulting modifications were implemented in a key project of the Removable Products group
Mentored representatives of all product lines and provided assistance in troubleshooting efforts
Developed test benches - directed and random - to validate command sequences on firmware models of Confidential flash memory. These support stand-alone validation of the models
Transcribed sequences, ranging from basic reads to program failure recovery mechanisms, in SCAPA format to ensure faster shipping of low level memory sequences to firmware divisions
Implemented python based mechanism for regression testing of all SCAPA test cases and regular monitoring of errors
Overhauled older method of running SCAPA tests and introduced a simple interface in Windows powered by python, that would automatically generate tests depending on the user’s selection of memory configuration and sequence

Confidential

Verification Engineer

Responsibilities:

Joint owner of test plan for switch fabric
Created inject based tests to validate features such as flow control, bubbles, etc.
Performance Automation tests to simulate real world behavior of the Transport layer
Enable efficient transaction query based coverage infrastructure for Crossbar switch
Implement test-cases, modified checkers and injectors, at the block level
Ensure coverage closure (functional) at the block level
Triaging regression failures for multiple blocks on a regular basis

Verification Engineer

Confidential

Responsibilities:

Actively involved in incorporating efficient coverage models for verification of wireless chipset
Development of Verification IP for AMBA-AHB
Debug and Regression testing of synthesized net-lists of high definition Audio Controller

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