SUMMARY

• To obtain a position that will enable me to use my skill in high speed digital IC/ASIC/SoC/Application/project management and network system validation/Bring - up
• Extensive experience in PCB debug (Allegro), SI analysis, diagnosis, and validation with
• High Band-Width scope, PCIe analyzer, Logic analyzer and ChipScope
• Experience with SLTK software for high speed bus signal integrity validation and DVT(Design Verification Test)
• FPGA design with Quartus/ISE software
• CPU(x86) design and development
• Network processor development with L2/L3 switching
• Experience in ASIC design with complete timing-closure process, designing in C environment and chip debug with SystemVerilog. Verilog and VHDL.
• Experience in circuit design with HSPICE and silicon debug and characterization
• Good working knowledge of design of SRAM, DDR, PCIe, SerDes, Interlaken, PLL, I2C, XAUI, SGMII, CSCI, iCSCI, NVMe

PROFESSIONAL EXPERIENCE

Confidential, Milpitas CA

Network System Development

Responsibilities:

• Involved in developing ASR9K Route Switching Processor (RSP) Board. Mainly working on high-speed signal integrity validation, board level debugs along with massive bandwidth progression for three different products.
• Serdes tuning and SI validation
• various FPGA, ASIC, PHY and CPU, such as XAUI, SGMII, PCIe Gen 1/2, Interlaken (Cisco proprietary bus), SSD/SATA/USB, ASIC fabric switch.
• between RSP card, Fabric switch card and Line cards, at 7.5Gbps per SerDes, 7.5 Gbps x8=55Gbps per fabric Channel, 14 Fabric channel per line card, 20 line card per chassis ASR9K, total 2240 Serdes tuning using TI’s SLTK tool.
• high speed data-punt path virtual output queuing, unicast-flood packet replicate at 6.25Gbps per SerDes, 55Gbps per fabric Channel using TI’s SLTK tool.
• PCIe Gen 1/2 between Intel PCH and FPGA(Xilinx Virtex 6/5), ASIC, Intel 10/1GE PHY, Fabric card (FC)
• Designed test fixture boards to provide a nearly transparent connection between the circuit
• board under test, and theSImeasurementequipment.
• serial interface up to 6.25G x16 ASIC network memory.
• between peer RSP through backplane for system arbitration, GE offload EOBC, and Fabric card (FC)
• SITools and Models - Hyperlynx, HSPICE, SIwave, PLT, Scrutiny, IBIS, S-parameters
• 10G SFP+ ports optical and electrical tests validation debug
• Data punt error of Interlaken 3.25Gbpsx4 interface debug between ASIC and FPGA(Xilinx Virtex 6)
• The 10G PHY AMCC QT2025 interfaces between the SFP+ port and a four lane XAUI (each direction) to the Broadcom BCM56334 (4x 10G,24x1G) Ethernet switch debug
• FPGA design/debug for I2C controller.
• EDVT(Electronic Design Verification Test)
• Eight corners (-5C and 55C) Temperature/ Frequency (CPU clock only)/Voltage cycle including:

Confidential

Quality Asurance

Responsibilities:

• Coordinated IP vendor development, scheduled the project milestones and set up delivery methodology for various IP.
• Coordinated fab daily production for quality monitor with CPK tool
• Address customers issues by providing guidance, detailed debug and engagement, and drive issues to resolution
• Supervised a team to monitor customer’s complaints and responded swiftly the issues with 8-D system in order to preserve customer’s satisfaction and pave the way to long-term business success.

Senior Design Engineering Manager

Confidential, CA

Responsibilities:

• Managed the digital design group.
• Joined marketing for product definition, evaluated tools and brought up the design methodology.
• Defined the milestones of product development. Coordinated with IP vendors.
• Supervised the team for cross-functional dept interfaces and to integrate the whole chip. Worked with product marketing to review product release note and application specifications
• Joined the leading company in Voice Over ATM industry to develop the complicated telephony gateway system to route the data and voice simultaneously through ATM and CLASS 5 switch
• Mainly responsible for two FPGA designs by using Quartus Software. Also, the real telephony traffic was generated to verify the quality of voice.
• System arbitration card: To maintain the fairness of traffic distribution between downstream and upstream to achieve 99.999% completion rate.
• ATM line card: To shape the ATM traffic and reassembly the ATM cells carrying the Voice and data Buffer management was implemented to optimize the voice cell drop rate.

Sr Engineer

Confidential

Responsibilities:

• Joined the company as a founding member to develop the high speed network processor to process high speed frames, ATM cells and packets at 622Mbps data rate, full duplex 66 MHz PCI and local bus to achieve OC-12 line rate, traffic policing and SoQ were incorporated
• The total gate count was about 800k plus memory with the deployment of the then-the-most advanced 0.35u technology.
• Coding with VHDL
• Chip verification with System Verilog and C environment
• Lead 10 engineers starting from coding functional mode, gate-level design, post-layout simulation, back-end tape-out and final chip debug.
• Worked with the team as a key member to catch Intel’s attention to acquire.