ASIC Design Engineer Resume Sunnyvale, California - Hire IT People

SUMMARY

ASIC Engineer with 9 years experience in SoC development seeking a challenging position.
Possess solid technical capabilities in analysis, design, troubleshoot, and test, in addition to leadership capacity in managing projects, products, and teams.

TECHNICAL SKILLS

Applications: Mentor 0in Lint/CDC, Spyglass Lint, SpringSoft Verdi, Synopsys PrimeTime (PX), Synopsys VCS, Cadence NCSim, Mentor ModelSim, Calypto Power Pro, ARM Real Viewer, Synplify, Xilinx ISE, Altera Quartus II, Lattice ispLEVER, Allegro Schematic/PCB Design, Matlab, LabView

Languages: Verilog, VHDL, C, Perl, Java

PROFESSIONAL EXPERIENCE

Confidential, Sunnyvale, California

ASIC Design Engineer

Responsibilities:

Coordinated projects’ key deliverables, schedules, and priorities meeting tapeout schedule.
Involved in chip development life cycle encompassing research phase, front end design, back end support, silicon bring up, and production ramping.
Developed system data paths, ARM M4 subsystem, system pinout architecture, low power design, system top level integration, and lint/cdc flow.
Designed and implemented DFT flow for digital logic, analog IP, IO, BIST, and burn in.
Led effort in reviewing STA, MVRC, LEC, and DFT violation reports, and coordinating ECO cycles.
Spearheaded effort to resolve silicon power consumption issue, and retention coverage in production.
Collaborated with multi - functional teams to determine constraints and limitation of design and flow.
Responsible for the implementation of functional test flow in production to increase efficiency.

Confidential, Santa Clara, California

ASIC Design Engineer

Responsibilities:

Responsible for the design, integration, verification, STA, bench validation, and production vector.
Designed and implemented system clock tree, interrupt scheme, and OTPs for RSA authentication.
Implemented DRO and AVS to determine silicon’s process corner resulting in higher yield.
Developed flow for power consumption estimation during active and lowest leakage modes.
Collaborated with cross functional teams in verification, validation, and production efforts.
Interfaced with customers for issues resolution, and product presentations.

Confidential, Mountain View, California

Hardware Engineer

Responsibilities:

Designed high bandwidth data decimation and distribution across FPGAs, ADCs, and memories.
Modeled in Verilog an ultrahigh bandwidth, multi-clocked ADC chip for end to end simulation.
Analyzed, troubleshot, and tested whole system end product.
Collaborated with various teams to develop testing criteria for existing HDD testers, and prototypes.
Resolved customers’ issues, and coordinated training on system hardware and software.

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Asic Design Engineer Resume

Sunnyvale, CaliforniA

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