SUMMARY:

• Phrase based Speech Recognition, Acoustic Signature classification, Mapping High Performance Computing (HPC) and Digital Signal Processing (DSP) algorithms to FPGA and GPU, accelerating algorithms using OpenCL/CUDA and targeting many - core/multi-core processors, GPUs, and FPGAs, Electro-optical and Infra-red image processing.

PROFESSIONAL EXPERIENCE:

Confidential

Research Engineer

Responsibilities:

• Presently developing accelerated algorithms targeting Nvidia GPUs and Xeon Phis’ to denoise Mid-wave Infra-red images, for detecting and replacement of bad pixels, non-uniformity correction, and doming correction using OpenCL/CUDA. Non-uniformity correction, bad pixel detection and correction, image to image registration, temporal Kalman filtering, spatial adaptive Weiner filtering and super-resolution (up-sampling) are some of teh functional blocks used in this effort.
• Worked on a project to reconstruct citywide 3D models from multiple electro optical images taken from UAVs. This is a part of an effort to develop autonomous navigation algorithms, visual GPS, etc. Some of teh work involved developing optical -flow, motion estimation, establishing correspondence, projection, Euclidean distance estimation, etc. for teh US Air Force Research Labs.
• Developed teh toolsets to preprocess large format Infra-red and Electro Optical images and compress aboard a UAV using JPEG2000 for teh US Air Force Research Labs. Teh system included FPGA based accelerated compression, transmission to a ground station, storing in a database and a viewer client that decompressed teh images. Bad pixel detection, bad pixel replacement, doming correction, dynamic range correction algorithms were also implemented.
• Developed hardware acceleration models for teh SRC FPGA system for Harris corner detection and optical flow.
• Worked on computing teh separability metrics for large image data sets. These metrics are used to determine teh performance of various image classification/object detection algorithms. These algorithms are designed for Electro-Optical as well as Infra-Red and Radar images.
• Worked on computing teh uncertainty of a computed homographies when multiple homographies are present. Kalman filter predictions based computations are also being used for this effort. Realistic Models are being developed so that they accurately represent teh uncertainty.
• Accelerated a reconstructed image quality assessment algorithm Mutual Correlation Coefficient (MCC) targeting a GPU. This achieved a speed up of approximately 10x.
• Accelerated teh image registration algorithms Speeded Up Robust Features (SURF) and Efficient Second-order Minimization (ESM) and a three frame differencing algorithm using CUDA and NPP libraries, which are parts of teh GATER moving object tracking system.
• Developed a vector quantization based image compression algorithm from concept (using matlab) to teh accelerated implementation (using OpenCL). These models are targeted for processing large aerial images.
• Developed accelerated OpenCL models for image Projection using Digital Elevation Maps (DEMs). All teh OpenCL models are being hosted on GPUs, many core (Xeon Phi) and multi core processors, and FPGAs.

Confidential

Senior Researcher

Responsibilities:

• Developed algorithms for an Image processing applications. Teh algorithms developed were in teh areas of image/video stabilization, object tracking, video compression using wavelet transform, optical flow analysis, multi virtual object analysis, and registration.
• Until February 2008, worked at teh Wright Patterson Air Force Base in teh Human TEMPEffectiveness Directorate for General Dynamics Inc. Teh work mostly involved in developing software for DSP algorithms in teh audio frequency range and classification of acoustic signatures of various helicopters.
• From Served as a Patent Reviewer. Basically, teh work involved reviewing patent applications that are submitted to teh Patent and Trademark Office.

Confidential

Senior Networking Researcher

Responsibilities:

• Developed a Direct Memory Access (DMA) Engine for teh Cray XD1 FPGA Environment
• As part of this project, a memory interface was developed that facilitates teh transfer of data between teh host and teh FPGA using DMA. This enabled a higher I/O bandwidth between teh host and teh FPGA and concurrent computing wif I/O transfers.
• Teh main focus of this project was to map graph theory based algorithms to FPGA. One key algorithm that was targeted was teh Floyd-Warshall algorithm to find teh All-Pair Shortest paths. Using FPGAs we were able to significantly reduce teh resources required to compute teh all pair shortest paths for a large weighted graph. This work was published in two highly reputed conferences.

Confidential, Dayton Ohio

Senior Engineer

Responsibilities:

• My responsibilities as project manager included writing proposals and winning SBIR contracts, setting goals for teh projects and achieving all objectives wifin budget and on time, supervising other engineers in my group and satisfying all teh targets of teh customer. In addition I was responsible for technology transfer, commercialization and interactions wif potentials customers/users. Some of teh projects and my responsibilities are listed below.
• TEMPPrincipal Investigator, DARPA SBIR Phase I & II, Voice Communication System In this effort we developed a phrase based speech recognition engine using Hidden Markov Models (HMM) and Artificial Neural Networks (ANN). These engines were trained using speech signals from subjects and tested against random speech.
• Senior Engineer, US Air Force SBIR Phase I, Wavelet Compression for Improved Synthetic Aperture Radar (SAR) Image Quality
• Senior Engineer, US Air Force SBIR Phase II, Virtual Objects Based Compression