OBJECTIVE:

• A challenging career as an Analog IC Design Engineer for Power Management Products

SUMMARY:

• More than 14 years of experience in full - custom CMOS analog/mixed-signal ICs design
• Hands-on Power Electronics systems design: PWM current-mode DC-to-DC converters, Buck and Boost converters, and Brushed DC Servo Motor Drivers
• Hands-on design in high speed low jitters PLL Clock Generators, clock synthesizers, Current-steering DACs and RAMDACs, Pipeline ADC, Differential Switched-capacitor Amplifier, Bandgap Voltage s, PTAT Current Generators, Constant-Current Balance circuits, high-accuracy Temperature Sensors, On-chip Linear Voltage Regulators, Voltage Comparators, Wideband Operational Amplifiers, LVPECL/LVDS/SSTL 18 IO cells, and HCSL Clock Buffers with deep submicron CMOS Technology
• Hands-on circuit design from initial product specification, architecture definition, circuit design and implemen-tation, circuit performance simulations, layout guidance and supervision, die size/power consumption/ accuracy /device matching/noise trade-off, package bonding diagram review, design review, tapeout documentation, silicon evaluation/debugging and bench characterization to product release
• Hands-on mask layout design on full-custom digital and analog cells using Virtuoso XL Layout Editor and backend checks such as LVS/DRC/ERC/Antenna/Electromigration(EM)/IR Drop/ESD Protection/Latch-up and violation fix
• EDA Tools on UNIX/Linux platforms: Cadence Virtuoso Schematic Editor and XL Layout Editor, Spectre and SpectreRF, Ocean script, Synopsys Hspice, HSIM, StarRC, Mentor’s Calibre nmLVS/nmDRC, Calibre RVE, Calibre xRC, Analog FastSPICE, and Apache Totem-MMX

PROFESSIONAL EXPERIENCE:

Confidential, San Diego, CA

Mixed-signal IC DESIGN CONTRACTOR

Responsibilities:

• Delivered next-generation high-speed(>4Gbps), low-power PHY SerDes blocks for SoCs in leading-edge CMOS process technology node at FinFET 10nm.
• Designed, simulated, and verified wireline transceiver building blocks including on-chip LDO Regulators, High Speed Rx Amps, Continueous-Time Linear Equalizer(CTLE), CML to CMOS Converter, and PLL LC-VCO
• Created test-bench schematics for high-speed electrical links and performed all necessary simulations to investigate TX Equalizer and RX CTLE techiniques to mitigate Inter-Symbol Interference(ISI).
• Created simulation and verification technical reports and held design reviews with peers/managers to show design meets spec targets and requirements
• Contributed to the following product’s design: Sanpdragon 835.

Confidential, San Jose, CA

Mixed-signal IC DESIGN CONTRACTOR

Responsibilities:

• Designed, simulated, and verified fully differential Switched-capacitor Variable Gain Amplifiers(VGA) for CMOS Image Sensors(CIS) using CMOS 65nm Technology
• Created test-bench schematics for CIS analog signal sampling and charge transfer path, performed functional verifications, switching timing verifications, and Linearity Analysis simulations of Switched-capacitor VGAs on all process-voltage-temperature(PVT) corners

Confidential, Sunnyvale, CA

Mixed-signal IC DESIGN CONTRACTOR

Responsibilities:

• Designed, simulated, and verified USB 3.0 (5 Gbps) and SATA 3 (6 Gbps) SerDes PHY building blocks for low power APUs/SOC, codenamed “Carrizo”, at the transistor circuit level on CMOS 28nm Technology
• Created test-bench schematics for Analog Front-End Receivers(AFE Rx), on-chip high speed Differential Clock Distribution Networks from PLL for clock buffers optimization, and ran Ocean scripts to cover all process-voltage-temperature(PVT) corners and Monte-Carlo analysis on post-layout netlists to improve silicon yield
• Performed Dynamic Power EMIR and Dynamic Signal EM analysis on SerDes Transmitter(Tx) using Apache’s Totem-MMX platform
• Created simulation and verification technical reports and related documentation required for design reviews and tape out sign off

Confidential

ANALOG IC DESIGN CONTRACTOR

Responsibilities:

• Designed and implemented On-chip Linear Voltage Regulators for USB 3.0 (5 Gbps) SerDes PHY IPs and PLL Clock Generators for USB 3.0 Solid-state Drive (SSD) Controllers using CMOS 0.13um/1.2V/3.3V General Purpose Process Technology

Confidential, Santa Clara, CA

SENIOR ANALOG IC DESIGN ENGINEER

Responsibilities:

• Designed and implemented Low Power Broadband Programmable Gain Amplifiers (PGA), Active RF Splitter. Active Balun, high frequency buffers, and Temperature Sensor for RF Active BandPass filters with frequency band covering DVB-H, GSM, GPS, and XM Radio applications, using CMOS 0.18um/1.8V MSRF Technology

Confidential, Santa Clara, CA

SENIOR MIXED-SIGNAL IC DESIGN ENGINEER

Responsibilities:

• Managed and supervised a design team to develop PLL Zero Delay Buffers (ASM5CVF857,ASM5CUA877) for Registered ECC DDR and DDR2 DIMMs applications using CMOS 0.25um/2.5V and 0.18um/1.8V technology respectively
• Designed and delivered a series of low phase noise and low jitter Programmable Spread Spectrum PLL Clock Generators (with VCO frequency from 400MHz to 1.2GHz) for LCD Displays, PCI-Express Gen2, and portable consumer Video/Audio applications using CMOS 0.18um/1.8V/3.3V Technology
• Designed and implemented IO Cells, Power/Ground Pads, and IO Pad Rings necessary for good signal integrity and providing successful ESD robust protection

Confidential, Sunnyvale, CA

MEMBER OF TECHNICAL STAFF

Responsibilities:

• Designed and implemented on-chip 1.8GHz low jitter PLL, PECL Clock Receiver, Temperature Sensors, and Process Control Monitors for UltraSPARC III series CPUs using CMOS 0.13um and 0.16um Copper (Low Voltage) Technology

Confidential, Santa Clara, CA

STAFF ANALOG IC DESIGN ENGINEER

Responsibilities:

• Accomplished the design and delivery of embedded 12-bit Current-steering Tx-DACs for Asymmetric Digital Subscriber Line ( ADSL ) analog front-end ICs, I80134 and 80234, using 0.35um/0.25um 3.3V Mixed-mode CMOS Technology

Confidential, Sunnyvale, CA

STAFF MIXED-SIGNAL IC DESIGN ENGINEER

Responsibilities:

• Accomplished the design and delivery of 1) A 250MHz 3 X 8-bit embedded RAMDAC 2) A series of on-chip low jitters PLL clock generators with VCO frequency from 250MHz to 600MHz using Low Power Deep Submicron (0.35um/3.3V and 0.25um/2.5V) CMOS Technology for multimedia ASIC products in optical storage and consumer electronics applications
• Contributed to the following products’ design: OTI-317 WARP5 3D Graphics chip, OTI-9325 Integrated CD-ROM Controller, OTI-257 MPEG1 Video/Audio Decoder, and OTI-226 TroikaCSS DVD Decoder